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@@ -1,918 +1,520 @@
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-#include "drv_usart.h"
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-#include "rkfifo.h"
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-#include "stm32f4xx.h"
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-#include "string.h"
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#include "board.h"
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+#include "hard_hdma_int.h"
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+#include "hpm_uart_drv.h"
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+#include "hpm_dmamux_drv.h"
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+#include "hpm_dma_drv.h"
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+#include "hpm_gpio_drv.h"
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+#include "hpm_clock_drv.h"
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+#include "rkfifo.h"
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+#include <string.h>
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+/* ========== 配置宏定义 ========== */
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+#ifndef UART_RX_FIFO_BUFFER_LEN
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+#define UART_RX_FIFO_BUFFER_LEN 256
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+#endif
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-static inline int _stm32_uart_rcc_enable(USART_TypeDef *uartx)
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-{
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- int ret = 0;
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- switch ((uint32_t)uartx)
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- {
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- case (uint32_t)USART1:
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- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
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- break;
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- case (uint32_t)USART2:
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- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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- break;
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- case (uint32_t)USART3:
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- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
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- break;
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- case (uint32_t)UART4:
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- RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
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- break;
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- case (uint32_t)UART5:
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- RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
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- break;
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- case (uint32_t)USART6:
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- RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
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- break;
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-
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- default:
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- ret = -1;
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- break;
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- }
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- return ret;
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-}
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-
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-static inline int _stm32_dma_rcc_enable(DMA_Stream_TypeDef *tx_dma)
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-{
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- int ret = 0;
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- switch ((uint32_t)tx_dma)
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- {
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- case (uint32_t)DMA1_Stream0:
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- case (uint32_t)DMA1_Stream1:
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- case (uint32_t)DMA1_Stream2:
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- case (uint32_t)DMA1_Stream3:
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- case (uint32_t)DMA1_Stream4:
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- case (uint32_t)DMA1_Stream5:
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- case (uint32_t)DMA1_Stream6:
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- case (uint32_t)DMA1_Stream7:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
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- break;
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-
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- case (uint32_t)DMA2_Stream0:
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- case (uint32_t)DMA2_Stream1:
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- case (uint32_t)DMA2_Stream2:
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- case (uint32_t)DMA2_Stream3:
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- case (uint32_t)DMA2_Stream4:
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- case (uint32_t)DMA2_Stream5:
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- case (uint32_t)DMA2_Stream6:
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- case (uint32_t)DMA2_Stream7:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
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- break;
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-
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- default:
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- ret = -1;
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- break;
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- }
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+#ifndef UART_TX_FIFO_BUFFER_LEN
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+#define UART_TX_FIFO_BUFFER_LEN 256
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+#endif
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- return ret;
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-}
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+#ifndef UART_TX_DMA_BUFFER_LEN
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+#define UART_TX_DMA_BUFFER_LEN 1024
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+#endif
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-static inline int _stm32_gpio_rcc_enable(GPIO_TypeDef *port)
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-{
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- int ret = 0;
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- switch ((uint32_t)port)
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- {
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- case (uint32_t)GPIOA:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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- break;
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- case (uint32_t)GPIOB:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
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- break;
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- case (uint32_t)GPIOC:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
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- break;
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- case (uint32_t)GPIOD:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
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- break;
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- case (uint32_t)GPIOE:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE);
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- break;
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- case (uint32_t)GPIOF:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE);
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- break;
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- case (uint32_t)GPIOG:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE);
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- break;
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- case (uint32_t)GPIOH:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOH, ENABLE);
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- break;
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- case (uint32_t)GPIOI:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOI, ENABLE);
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- break;
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- case (uint32_t)GPIOJ:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
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- break;
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- case (uint32_t)GPIOK:
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- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOK, ENABLE);
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- break;
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- default:
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- ret = -1;
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- break;
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- }
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- return ret;
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-}
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+/* ========== 外部DMA完成标志声明 ========== */
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+extern bool uart1_tx_dma_done;
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+extern bool uart2_tx_dma_done;
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+extern bool uart3_tx_dma_done;
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+extern bool uart4_tx_dma_done;
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+extern bool uart5_tx_dma_done;
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+extern bool uart6_tx_dma_done;
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+
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+/* ========== 结构体定义 ========== */
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+struct _uart_config {
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+ UART_Type *uart_base; /* UART基地址 */
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+ uart_intr_enable_t uart_irq_mask; /* UART中断掩码 */
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+ uint8_t uart_irq_num; /* 中断号 */
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+
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+ /* GPIO配置 */
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+ uint8_t tx_port; /* TX端口: 0-9 (GPIOA-GPIOJ) */
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+ uint8_t tx_pin; /* TX引脚 */
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+ uint8_t rx_port; /* RX端口 */
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+ uint8_t rx_pin; /* RX引脚 */
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+ uint8_t tx_af; /* TX复用功能 */
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+ uint8_t rx_af; /* RX复用功能 */
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+
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+ /* DMA配置 */
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+ DMA_Type *dma_base; /* DMA控制器基地址 */
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+ DMAMUX_Type *dma_mux_base; /* DMA MUX */
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+ uint8_t dma_enable; /* DMA 使能 (修正拼写) */
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+ uint8_t dma_channel; /* DMA通道 */
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+ uint8_t dma_irq_num; /* DMA中断号 */
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+ uint8_t dma_request; /* DMA请求源 */
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+
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+ /* 缓冲区 */
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+ uint8_t *tx_fifo_buff; /* TX FIFO缓冲区 */
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+ uint32_t tx_fifo_buff_size; /* TX FIFO大小 */
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+ uint8_t *rx_fifo_buff; /* RX FIFO缓冲区 */
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+ uint32_t rx_fifo_buff_size; /* RX FIFO大小 */
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+
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+ /* DMA缓冲区 */
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+ uint8_t *dma_tx_buff; /* DMA发送缓冲区 */
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+ uint32_t dma_tx_buff_size; /* DMA发送缓冲区大小 */
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+
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+ /* 内部使用 */
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+ rkfifo_t tx_fifo; /* TX FIFO */
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+ rkfifo_t rx_fifo; /* RX FIFO */
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+ volatile uint8_t dma_busy; /* DMA发送忙标志 */
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+};
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-static inline uint16_t _stm32_get_pinaf(uint16_t pin)
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-{
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- uint16_t ret = 0xff;
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- switch (pin)
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- {
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- case GPIO_Pin_0:
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- ret = GPIO_PinSource0;
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- break;
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- case GPIO_Pin_1:
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- ret = GPIO_PinSource1;
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- break;
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- case GPIO_Pin_2:
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- ret = GPIO_PinSource2;
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- break;
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- case GPIO_Pin_3:
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- ret = GPIO_PinSource3;
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- break;
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- case GPIO_Pin_4:
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- ret = GPIO_PinSource4;
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- break;
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- case GPIO_Pin_5:
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- ret = GPIO_PinSource5;
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- break;
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- case GPIO_Pin_6:
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- ret = GPIO_PinSource6;
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- break;
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- case GPIO_Pin_7:
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- ret = GPIO_PinSource7;
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- break;
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- case GPIO_Pin_8:
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- ret = GPIO_PinSource8;
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- break;
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- case GPIO_Pin_9:
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- ret = GPIO_PinSource9;
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- break;
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- case GPIO_Pin_10:
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- ret = GPIO_PinSource10;
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- break;
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- case GPIO_Pin_11:
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- ret = GPIO_PinSource11;
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- break;
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- case GPIO_Pin_12:
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- ret = GPIO_PinSource12;
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- break;
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- case GPIO_Pin_13:
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- ret = GPIO_PinSource13;
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- break;
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- case GPIO_Pin_14:
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- ret = GPIO_PinSource14;
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- break;
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- case GPIO_Pin_15:
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- ret = GPIO_PinSource15;
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- break;
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- default:
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- break;
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- }
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- return ret;
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-}
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+struct _uart_ops {
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+ int (*init)(struct _uart_config *config, uint32_t baudrate);
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+ uint32_t (*read)(struct _uart_config *config, void *data, uint32_t len);
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+ uint32_t (*write)(struct _uart_config *config, const void *data, uint32_t len);
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+};
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-static inline uint8_t _stm32_get_uartaf(USART_TypeDef *uartx)
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-{
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- uint8_t ret = 0;
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- switch ((uint32_t)uartx)
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- {
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- case (uint32_t)USART1:
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- ret = GPIO_AF_USART1;
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- break;
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- case (uint32_t)USART2:
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- ret = GPIO_AF_USART2;
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- break;
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- case (uint32_t)USART3:
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- ret = GPIO_AF_USART3;
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- break;
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- case (uint32_t)UART4:
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- ret = GPIO_AF_UART4;
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- break;
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- case (uint32_t)UART5:
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- ret = GPIO_AF_UART5;
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- break;
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- case (uint32_t)USART6:
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- ret = GPIO_AF_USART6;
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- break;
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-
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- default:
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- ret = -1;
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- break;
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- }
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- return ret;
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-}
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+struct _uart_device {
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+ struct _uart_config *config;
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+ struct _uart_ops *ops;
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+};
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-static int _uart_config(struct stm32_uart_config *uart, uint32_t bps)
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-{
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- int ret = 0;
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- _stm32_uart_rcc_enable(uart->uartx);
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- _stm32_gpio_rcc_enable(uart->_tx_port);
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- _stm32_gpio_rcc_enable(uart->_rx_port);
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-
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- USART_DeInit(uart->uartx);
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- GPIO_InitTypeDef GPIO_InitStructure;
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- GPIO_StructInit(&GPIO_InitStructure);
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- GPIO_InitStructure.GPIO_Pin = uart->_tx_pin;
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- GPIO_InitStructure.GPIO_Speed = GPIO_High_Speed;
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- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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- GPIO_Init(uart->_tx_port, &GPIO_InitStructure);
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- GPIO_InitStructure.GPIO_Pin = uart->_rx_pin;
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- GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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- GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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- GPIO_Init(uart->_rx_port, &GPIO_InitStructure);
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-
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- GPIO_PinAFConfig(uart->_rx_port, _stm32_get_pinaf(uart->_rx_pin), _stm32_get_uartaf(uart->uartx));
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- GPIO_PinAFConfig(uart->_tx_port, _stm32_get_pinaf(uart->_tx_pin), _stm32_get_uartaf(uart->uartx));
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-
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- USART_InitTypeDef USART_InitStructure;
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- USART_StructInit(&USART_InitStructure);
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- USART_InitStructure.USART_BaudRate = bps;
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-
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- USART_Init(uart->uartx, &USART_InitStructure);
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-
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- if (uart->_rx_dma == NULL)
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- {
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- /* 采用中断式接收 */
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- USART_ITConfig(uart->uartx, USART_IT_RXNE, ENABLE);
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+/* ========== 辅助函数:获取DMA完成标志指针 ========== */
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+static bool* _get_dma_done_flag(UART_Type *uart_base)
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+{
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+ if (uart_base == HPM_UART1) {
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+ return &uart1_tx_dma_done;
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+ } else if (uart_base == HPM_UART2) {
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+ return &uart2_tx_dma_done;
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+ } else if (uart_base == HPM_UART3) {
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+ return &uart3_tx_dma_done;
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+ } else if (uart_base == HPM_UART4) {
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+ return &uart4_tx_dma_done;
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+ } else if (uart_base == HPM_UART5) {
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+ return &uart5_tx_dma_done;
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+ } else if (uart_base == HPM_UART6) {
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+ return &uart6_tx_dma_done;
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}
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- else
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- {
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- /* 采用 dma 式接收*/
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- USART_ITConfig(uart->uartx, USART_IT_IDLE, ENABLE);
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+ return NULL;
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+}
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+
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+/* ========== 时钟使能函数 ========== */
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+static void _uart_clock_enable(UART_Type *uart_base)
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+{
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+ if (uart_base == HPM_UART0) {
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+ clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
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+ clock_add_to_group(clock_uart0, 0);
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+ } else if (uart_base == HPM_UART1) {
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+ clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
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+ clock_add_to_group(clock_uart1, 0);
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+ } else if (uart_base == HPM_UART2) {
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+ clock_set_source_divider(clock_uart2, clk_src_osc24m, 1);
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+ clock_add_to_group(clock_uart2, 0);
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+ } else if (uart_base == HPM_UART3) {
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+ clock_set_source_divider(clock_uart3, clk_src_osc24m, 1);
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+ clock_add_to_group(clock_uart3, 0);
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+ } else if (uart_base == HPM_UART4) {
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+ clock_set_source_divider(clock_uart4, clk_src_osc24m, 1);
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+ clock_add_to_group(clock_uart4, 0);
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+ } else if (uart_base == HPM_UART5) {
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+ clock_set_source_divider(clock_uart5, clk_src_osc24m, 1);
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+ clock_add_to_group(clock_uart5, 0);
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+ } else if (uart_base == HPM_UART6) {
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+ clock_set_source_divider(clock_uart6, clk_src_osc24m, 1);
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+ clock_add_to_group(clock_uart6, 0);
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+ } else if (uart_base == HPM_UART7) {
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+ clock_set_source_divider(clock_uart7, clk_src_osc24m, 1);
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+ clock_add_to_group(clock_uart7, 0);
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}
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-
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- USART_Cmd(uart->uartx, ENABLE);
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-
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- return ret;
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}
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-static int _uart_dma_config(struct stm32_uart_config *uart)
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|
-{
|
|
|
- int ret = 0;
|
|
|
- DMA_InitTypeDef dma_conf;
|
|
|
-
|
|
|
- /* tx dma config */
|
|
|
- if (uart->_tx_dma && uart->_dma_tx_buff)
|
|
|
- {
|
|
|
- _stm32_dma_rcc_enable(uart->_tx_dma);
|
|
|
- DMA_DeInit(uart->_tx_dma);
|
|
|
- while (DMA_GetCmdStatus(uart->_tx_dma) != DISABLE)
|
|
|
- {
|
|
|
- };
|
|
|
- DMA_StructInit(&dma_conf);
|
|
|
- dma_conf.DMA_Channel = uart->_tx_dma_channel;
|
|
|
- dma_conf.DMA_PeripheralBaseAddr = (u32)(&(uart->uartx->DR));
|
|
|
- dma_conf.DMA_Memory0BaseAddr = (u32)uart->_dma_tx_buff;
|
|
|
- dma_conf.DMA_DIR = DMA_DIR_MemoryToPeripheral;
|
|
|
- dma_conf.DMA_BufferSize = (uint32_t)uart->_dma_tx_buff;
|
|
|
- dma_conf.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
|
|
- dma_conf.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
|
|
- dma_conf.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
|
|
- dma_conf.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
|
|
|
- dma_conf.DMA_Mode = DMA_Mode_Normal;
|
|
|
- dma_conf.DMA_Priority = DMA_Priority_Medium;
|
|
|
- dma_conf.DMA_FIFOMode = DMA_FIFOMode_Disable;
|
|
|
- dma_conf.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
|
|
|
- dma_conf.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
|
|
- dma_conf.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
|
|
- DMA_Init(uart->_tx_dma, &dma_conf);
|
|
|
- DMA_ITConfig(uart->_tx_dma, DMA_IT_TC, ENABLE);
|
|
|
- DMA_ITConfig(uart->_tx_dma, DMA_IT_TE, ENABLE);
|
|
|
- DMA_Cmd(uart->_tx_dma, DISABLE);
|
|
|
- // 串口采用 dma 发送
|
|
|
- USART_DMACmd(uart->uartx, USART_DMAReq_Tx, ENABLE);
|
|
|
- //等待关闭使能完成
|
|
|
- while (DMA_GetCmdStatus(uart->_tx_dma) != DISABLE)
|
|
|
- {
|
|
|
- };
|
|
|
- }
|
|
|
-
|
|
|
- /* rx dma config */
|
|
|
- if (uart->_rx_dma && uart->_dma_rx_buff)
|
|
|
- {
|
|
|
- // 配置串口的 dma 接收
|
|
|
- _stm32_dma_rcc_enable(uart->_rx_dma);
|
|
|
- DMA_StructInit(&dma_conf);
|
|
|
- DMA_DeInit(uart->_rx_dma);
|
|
|
- while (DMA_GetCmdStatus(uart->_rx_dma) != DISABLE)
|
|
|
- {
|
|
|
- };
|
|
|
- dma_conf.DMA_Channel = uart->_rx_dma_channel;
|
|
|
- dma_conf.DMA_PeripheralBaseAddr = (u32)(&uart->uartx->DR);
|
|
|
- dma_conf.DMA_Memory0BaseAddr = (u32)uart->_dma_rx_buff;
|
|
|
- dma_conf.DMA_DIR = DMA_DIR_PeripheralToMemory;
|
|
|
- dma_conf.DMA_BufferSize = uart->_dma_rx_buff_size;
|
|
|
- dma_conf.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
|
|
- dma_conf.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
|
|
- dma_conf.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
|
|
- dma_conf.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
|
|
|
- dma_conf.DMA_Mode = DMA_Mode_Normal;
|
|
|
- dma_conf.DMA_Priority = DMA_Priority_High;
|
|
|
- dma_conf.DMA_FIFOMode = DMA_FIFOMode_Disable;
|
|
|
- dma_conf.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
|
|
|
- dma_conf.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
|
|
- dma_conf.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
|
|
- DMA_Init(uart->_rx_dma, &dma_conf);
|
|
|
- DMA_ITConfig(uart->_rx_dma, DMA_IT_TC, ENABLE);
|
|
|
- DMA_ITConfig(uart->_rx_dma, DMA_IT_TE, ENABLE);
|
|
|
- DMA_Cmd(uart->_rx_dma, ENABLE);
|
|
|
- /* 串口采用 dma 接收 */
|
|
|
- USART_DMACmd(uart->uartx, USART_DMAReq_Rx, ENABLE);
|
|
|
- while (DMA_GetCmdStatus(uart->_rx_dma) != ENABLE)
|
|
|
- {
|
|
|
- };
|
|
|
+/* ========== DMA时钟使能 ========== */
|
|
|
+static void _dma_clock_enable(DMA_Type *dma_base)
|
|
|
+{
|
|
|
+ /* HDMA 时钟来源于系统总线时钟(AHB),已默认使能 */
|
|
|
+ (void)dma_base;
|
|
|
+}
|
|
|
+
|
|
|
+/* ========== GPIO配置 ========== */
|
|
|
+static void _uart_gpio_config(UART_Type *uart_base)
|
|
|
+{
|
|
|
+ if (uart_base == HPM_UART1) {
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_UART1_TXD;
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART1_RXD;
|
|
|
+ } else if (uart_base == HPM_UART2) {
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_UART2_RXD;
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_UART2_TXD;
|
|
|
+ } else if (uart_base == HPM_UART3) {
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_UART3_RXD;
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_UART3_TXD;
|
|
|
+ } else if (uart_base == HPM_UART4) {
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_UART4_RXD;
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_UART4_TXD;
|
|
|
+ } else if (uart_base == HPM_UART5) {
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_UART5_TXD;
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_UART5_RXD;
|
|
|
+ } else if (uart_base == HPM_UART6) {
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_UART6_RXD;
|
|
|
+ HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_UART6_TXD;
|
|
|
}
|
|
|
-
|
|
|
- return ret;
|
|
|
}
|
|
|
|
|
|
-void _uart_nvic_config(struct stm32_uart_config *uart)
|
|
|
-{
|
|
|
- NVIC_InitTypeDef NVIC_InitStructure;
|
|
|
-
|
|
|
- NVIC_InitStructure.NVIC_IRQChannel = uart->_uart_irq_channel;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
|
|
- NVIC_Init(&NVIC_InitStructure);
|
|
|
-
|
|
|
- if (uart->_rx_dma && uart->_dma_rx_buff)
|
|
|
- {
|
|
|
- NVIC_InitStructure.NVIC_IRQChannel = uart->_rx_dma_irq_channel;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
|
|
- NVIC_Init(&NVIC_InitStructure);
|
|
|
+/* ========== UART配置 ========== */
|
|
|
+static int _uart_config(struct _uart_config *config, uint32_t baudrate)
|
|
|
+{
|
|
|
+ uart_config_t uart_cfg;
|
|
|
+ uint32_t uart_clock_freq = 0;
|
|
|
+
|
|
|
+ /* 使能时钟 */
|
|
|
+ _uart_clock_enable(config->uart_base);
|
|
|
+
|
|
|
+ /* 配置GPIO */
|
|
|
+ _uart_gpio_config(config->uart_base);
|
|
|
+
|
|
|
+ /* 获取UART时钟频率 */
|
|
|
+ if (config->uart_base == HPM_UART0) {
|
|
|
+ uart_clock_freq = clock_get_frequency(clock_uart0);
|
|
|
+ } else if (config->uart_base == HPM_UART1) {
|
|
|
+ uart_clock_freq = clock_get_frequency(clock_uart1);
|
|
|
+ } else if (config->uart_base == HPM_UART2) {
|
|
|
+ uart_clock_freq = clock_get_frequency(clock_uart2);
|
|
|
+ } else if (config->uart_base == HPM_UART3) {
|
|
|
+ uart_clock_freq = clock_get_frequency(clock_uart3);
|
|
|
+ } else if (config->uart_base == HPM_UART4) {
|
|
|
+ uart_clock_freq = clock_get_frequency(clock_uart4);
|
|
|
+ } else if (config->uart_base == HPM_UART5) {
|
|
|
+ uart_clock_freq = clock_get_frequency(clock_uart5);
|
|
|
+ } else if (config->uart_base == HPM_UART6) {
|
|
|
+ uart_clock_freq = clock_get_frequency(clock_uart6);
|
|
|
+ } else if (config->uart_base == HPM_UART7) {
|
|
|
+ uart_clock_freq = clock_get_frequency(clock_uart7);
|
|
|
}
|
|
|
-
|
|
|
- if (uart->_tx_dma && uart->_dma_tx_buff)
|
|
|
- {
|
|
|
- NVIC_InitStructure.NVIC_IRQChannel = uart->_tx_dma_irq_channel;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
|
|
|
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
|
|
- NVIC_Init(&NVIC_InitStructure);
|
|
|
+
|
|
|
+ /* 配置UART */
|
|
|
+ uart_default_config(config->uart_base, &uart_cfg);
|
|
|
+ uart_cfg.baudrate = baudrate;
|
|
|
+ uart_cfg.word_length = word_length_8_bits;
|
|
|
+ uart_cfg.num_of_stop_bits = stop_bits_1;
|
|
|
+ uart_cfg.parity = parity_none;
|
|
|
+ uart_cfg.fifo_enable = true;
|
|
|
+ uart_cfg.dma_enable = config->dma_enable ? true : false;
|
|
|
+ uart_cfg.tx_fifo_level = uart_tx_fifo_trg_not_full;
|
|
|
+ uart_cfg.rx_fifo_level = uart_rx_fifo_trg_gt_three_quarters;
|
|
|
+ uart_cfg.src_freq_in_hz = uart_clock_freq;
|
|
|
+
|
|
|
+ uart_init(config->uart_base, &uart_cfg);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/* ========== DMA配置 ========== */
|
|
|
+static int _uart_dma_config(struct _uart_config *config)
|
|
|
+{
|
|
|
+ dma_handshake_config_t handshake_config;
|
|
|
+
|
|
|
+ if (config->dma_tx_buff == NULL) {
|
|
|
+ return -1;
|
|
|
}
|
|
|
+
|
|
|
+ /* 使能DMA时钟 */
|
|
|
+ _dma_clock_enable(config->dma_base);
|
|
|
+
|
|
|
+ /* 配置 DMAMUX */
|
|
|
+ dmamux_config(config->dma_mux_base,
|
|
|
+ DMA_SOC_CHN_TO_DMAMUX_CHN(config->dma_base, config->dma_channel),
|
|
|
+ config->dma_request,
|
|
|
+ true);
|
|
|
+
|
|
|
+ /* 配置 TX 握手参数 */
|
|
|
+ dma_default_handshake_config(config->dma_base, &handshake_config);
|
|
|
+ handshake_config.ch_index = config->dma_channel;
|
|
|
+ handshake_config.dst = (uint32_t)&config->uart_base->THR;
|
|
|
+ handshake_config.dst_fixed = true;
|
|
|
+ handshake_config.src = core_local_mem_to_sys_address(0, (uint32_t)config->dma_tx_buff);
|
|
|
+ handshake_config.src_fixed = false;
|
|
|
+ handshake_config.data_width = DMA_TRANSFER_WIDTH_BYTE;
|
|
|
+ handshake_config.size_in_byte = config->dma_tx_buff_size;
|
|
|
+
|
|
|
+ hpm_stat_t stat = dma_setup_handshake(config->dma_base, &handshake_config, false);
|
|
|
+ if (stat != status_success) {
|
|
|
+ printf("uart dma tx config error\r\n");
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-int uart_init(struct stm32_uart_config *uart, uint32_t bps)
|
|
|
+/* ========== NVIC中断配置 ========== */
|
|
|
+static void _uart_nvic_config(struct _uart_config *config)
|
|
|
{
|
|
|
- int ret = 0;
|
|
|
- rkfifo_init(&uart->_rx_fifo, uart->_rx_fifo_buff, uart->_rx_fifo_buff_size, 1);
|
|
|
- rkfifo_init(&uart->_tx_fifo, uart->_tx_fifo_buff, uart->_tx_fifo_buff_size, 1);
|
|
|
-
|
|
|
- _uart_config(uart, bps);
|
|
|
- _uart_dma_config(uart);
|
|
|
- _uart_nvic_config(uart);
|
|
|
-
|
|
|
- return ret;
|
|
|
+ /* 使能UART中断 */
|
|
|
+ uart_enable_irq(config->uart_base, config->uart_irq_mask);
|
|
|
+ intc_m_enable_irq_with_priority(config->uart_irq_num, 1);
|
|
|
+
|
|
|
+ /* 使能DMA中断 */
|
|
|
+ if (config->dma_enable) {
|
|
|
+ intc_m_enable_irq_with_priority(config->dma_irq_num, 1);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
-/**
|
|
|
- * @brief 串口发送数据
|
|
|
- *
|
|
|
- * @param uart 串口对象
|
|
|
- * @param pdata 发送的数据指针
|
|
|
- * @param len 发送的数据长度
|
|
|
- * @return uint32_t 实际发送的数据长度
|
|
|
- */
|
|
|
-static uint32_t uart_tx_data(struct stm32_uart_config *uart, const void *pdata, uint32_t len)
|
|
|
+/* ========== UART初始化 ========== */
|
|
|
+int _uart_init(struct _uart_config *config, uint32_t baudrate)
|
|
|
{
|
|
|
- assert_param(uart != NULL);
|
|
|
- assert_param(pdata != NULL);
|
|
|
- uint32_t ret = 0;
|
|
|
- if (len > 0)
|
|
|
- {
|
|
|
- /* 将数据压入 tx FIFO */
|
|
|
- ret = rkfifo_in(&uart->_tx_fifo, pdata, len);
|
|
|
-
|
|
|
- if (uart->_tx_dma)
|
|
|
- {
|
|
|
- /* dma 形式发送数据 */
|
|
|
- if ((USART_GetFlagStatus(uart->uartx, USART_FLAG_TXE) == SET) &&
|
|
|
- (USART_GetFlagStatus(uart->uartx, USART_FLAG_TC) == SET))
|
|
|
- {
|
|
|
- // fifo 中是否还有数据, 如果还有数据, 则读取到 dma buff 中并进行发送
|
|
|
- uint32_t count = rkfifo_out(&uart->_tx_fifo,
|
|
|
- uart->_dma_tx_buff,
|
|
|
- uart->_dma_tx_buff_size);
|
|
|
- if (count > 0)
|
|
|
- {
|
|
|
- DMA_SetCurrDataCounter(uart->_tx_dma, count);
|
|
|
- DMA_Cmd(uart->_tx_dma, ENABLE);
|
|
|
- }
|
|
|
- }
|
|
|
- }
|
|
|
- else
|
|
|
- {
|
|
|
- /* 中断形式发送数据 */
|
|
|
- USART_ITConfig(uart->uartx, USART_IT_TXE, ENABLE);
|
|
|
- }
|
|
|
+ /* 初始化FIFO */
|
|
|
+ rkfifo_init(&config->tx_fifo, config->tx_fifo_buff, config->tx_fifo_buff_size, 1);
|
|
|
+ rkfifo_init(&config->rx_fifo, config->rx_fifo_buff, config->rx_fifo_buff_size, 1);
|
|
|
+
|
|
|
+ /* 配置UART硬件 */
|
|
|
+ _uart_config(config, baudrate);
|
|
|
+
|
|
|
+ /* 配置DMA */
|
|
|
+ if (config->dma_enable) {
|
|
|
+ _uart_dma_config(config);
|
|
|
}
|
|
|
-
|
|
|
- return ret;
|
|
|
+
|
|
|
+ /* 配置中断 */
|
|
|
+ _uart_nvic_config(config);
|
|
|
+
|
|
|
+ config->dma_busy = 0;
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
- * @brief 串口读取数据
|
|
|
- *
|
|
|
- * @param uart 串口对象
|
|
|
- * @param pdata 数据读取输出 buffer
|
|
|
- * @param len 数据读取长度
|
|
|
- * @return uint32_t 实际读出的长度
|
|
|
+ * @brief 获取串口发送是否忙碌
|
|
|
*/
|
|
|
-static uint32_t uart_rx_data(struct stm32_uart_config *uart, void *pdata, uint32_t len)
|
|
|
-{
|
|
|
- assert_param(uart != NULL);
|
|
|
- assert_param(pdata != NULL);
|
|
|
-
|
|
|
- uint32_t ret = rkfifo_out(&uart->_rx_fifo, pdata, len);
|
|
|
- return ret;
|
|
|
-}
|
|
|
-
|
|
|
-static void _rxne_isr_callback(struct stm32_uart *uart)
|
|
|
-{
|
|
|
- assert_param(uart != NULL);
|
|
|
-
|
|
|
- USART_TypeDef *uartx = uart->_config->uartx;
|
|
|
- rkfifo_t *rxfifo = &uart->_config->_rx_fifo;
|
|
|
-
|
|
|
- uint8_t data;
|
|
|
- data = USART_ReceiveData(uartx) & 0xFF;
|
|
|
- /* 将接收到的数据压入 fifo */
|
|
|
- rkfifo_in(rxfifo, &data, 1);
|
|
|
- USART_ClearITPendingBit(uartx, USART_IT_RXNE);
|
|
|
-}
|
|
|
-
|
|
|
-static void _txe_isr_callback(struct stm32_uart *uart)
|
|
|
-{
|
|
|
- assert_param(uart != NULL);
|
|
|
-
|
|
|
- USART_TypeDef *usartx = uart->_config->uartx;
|
|
|
- rkfifo_t *txfifo = &uart->_config->_tx_fifo;
|
|
|
-
|
|
|
- if (USART_GetITStatus(usartx, USART_IT_TXE) == SET)
|
|
|
- {
|
|
|
- uint8_t c;
|
|
|
- if (rkfifo_out(txfifo, &c, 1))
|
|
|
- {
|
|
|
- /* fifo 有数据, 继续发送 */
|
|
|
- USART_SendData(usartx, c);
|
|
|
- }
|
|
|
- else
|
|
|
- {
|
|
|
- /* fifo 无数据, 关闭 txe 中断, 打开 TC 中断 */
|
|
|
- USART_ITConfig(usartx, USART_IT_TXE, DISABLE);
|
|
|
- USART_ITConfig(usartx, USART_IT_TC, ENABLE);
|
|
|
- }
|
|
|
-
|
|
|
- USART_ClearITPendingBit(usartx, USART_IT_TXE);
|
|
|
+bool usart_tx_isbusy(struct _uart_config *config)
|
|
|
+{
|
|
|
+ bool *dma_done_flag = _get_dma_done_flag(config->uart_base);
|
|
|
+
|
|
|
+ if (dma_done_flag) {
|
|
|
+ return !(*dma_done_flag);
|
|
|
}
|
|
|
+
|
|
|
+ return false;
|
|
|
}
|
|
|
|
|
|
-static void _tc_isr_callback(struct stm32_uart *uart)
|
|
|
-{
|
|
|
- assert_param(uart != NULL);
|
|
|
-
|
|
|
- USART_TypeDef *usartx = uart->_config->uartx;
|
|
|
-
|
|
|
- USART_ClearITPendingBit(usartx, USART_IT_TC);
|
|
|
-}
|
|
|
-
|
|
|
-static void _uart_isr_callback(struct stm32_uart *uart)
|
|
|
+void open_usart_dma_tx(struct _uart_config *config, uint32_t len)
|
|
|
{
|
|
|
- USART_TypeDef *uartx = uart->_config->uartx;
|
|
|
- DMA_Stream_TypeDef *rx_dma = uart->_config->_rx_dma;
|
|
|
- uint8_t *rx_dma_buff = uart->_config->_dma_rx_buff;
|
|
|
- uint32_t rx_dma_buff_size = uart->_config->_dma_rx_buff_size;
|
|
|
- rkfifo_t *rx_fifo = &uart->_config->_rx_fifo;
|
|
|
-
|
|
|
- if (USART_GetITStatus(uartx, USART_IT_RXNE) == SET)
|
|
|
- {
|
|
|
- _rxne_isr_callback(uart);
|
|
|
+ dma_handshake_config_t handshake_config;
|
|
|
+ bool *dma_done_flag = _get_dma_done_flag(config->uart_base);
|
|
|
+
|
|
|
+ /* 等待上次发送完成 */
|
|
|
+ uint32_t timeout = 1000000;
|
|
|
+ while (usart_tx_isbusy(config) && timeout--) {
|
|
|
+ __asm("nop");
|
|
|
}
|
|
|
- else if (USART_GetITStatus(uartx, USART_IT_TXE) == SET)
|
|
|
- {
|
|
|
- _txe_isr_callback(uart);
|
|
|
+
|
|
|
+ if (timeout == 0) {
|
|
|
+ /* 超时处理,复位DMA */
|
|
|
+ dma_abort_channel(config->dma_base, config->dma_channel);
|
|
|
+ if (dma_done_flag) {
|
|
|
+ *dma_done_flag = true;
|
|
|
+ }
|
|
|
}
|
|
|
- else if (USART_GetITStatus(uartx, USART_IT_TC) == SET)
|
|
|
- {
|
|
|
- _tc_isr_callback(uart);
|
|
|
+
|
|
|
+ /* 清除DMA完成标志 */
|
|
|
+ if (dma_done_flag) {
|
|
|
+ *dma_done_flag = false;
|
|
|
}
|
|
|
- else if (USART_GetITStatus(uartx, USART_IT_IDLE) == SET)
|
|
|
- {
|
|
|
- if (rx_dma)
|
|
|
- {
|
|
|
- DMA_Cmd(rx_dma, DISABLE);
|
|
|
- uint32_t dma_cnt = rx_dma_buff_size -
|
|
|
- DMA_GetCurrDataCounter(rx_dma);
|
|
|
- if (dma_cnt)
|
|
|
- {
|
|
|
- rkfifo_in(rx_fifo, &rx_dma_buff[0], dma_cnt);
|
|
|
+
|
|
|
+ /* 重新配置 TX 传输大小 */
|
|
|
+ dma_default_handshake_config(config->dma_base, &handshake_config);
|
|
|
+ handshake_config.ch_index = config->dma_channel;
|
|
|
+ handshake_config.dst = (uint32_t)&config->uart_base->THR;
|
|
|
+ handshake_config.dst_fixed = true;
|
|
|
+ handshake_config.src = core_local_mem_to_sys_address(0, (uint32_t)config->dma_tx_buff);
|
|
|
+ handshake_config.src_fixed = false;
|
|
|
+ handshake_config.data_width = DMA_TRANSFER_WIDTH_BYTE;
|
|
|
+ handshake_config.size_in_byte = len;
|
|
|
+
|
|
|
+ dma_setup_handshake(config->dma_base, &handshake_config, true);
|
|
|
+}
|
|
|
+
|
|
|
+/* ========== UART发送数据(DMA方式) ========== */
|
|
|
+static uint32_t uart_tx_data(struct _uart_config *config, const void *data, uint32_t len)
|
|
|
+{
|
|
|
+ uint32_t ret = 0;
|
|
|
+
|
|
|
+ if (len == 0) return 0;
|
|
|
+
|
|
|
+ /* 将数据压入TX FIFO */
|
|
|
+ ret = rkfifo_in(&config->tx_fifo, data, len);
|
|
|
+
|
|
|
+ if (config->dma_tx_buff != NULL && config->dma_enable) {
|
|
|
+ /* DMA方式发送 */
|
|
|
+ if (!config->dma_busy) {
|
|
|
+ /* DMA空闲,立即发送 */
|
|
|
+ uint32_t count = rkfifo_out(&config->tx_fifo,
|
|
|
+ config->dma_tx_buff,
|
|
|
+ config->dma_tx_buff_size);
|
|
|
+ if (count > 0) {
|
|
|
+ open_usart_dma_tx(config, count);
|
|
|
+ config->dma_busy = 1;
|
|
|
}
|
|
|
- //重新设置传输数据长度
|
|
|
- DMA_SetCurrDataCounter(rx_dma, uart->_config->_dma_rx_buff_size);
|
|
|
- //打开DMA
|
|
|
- DMA_Cmd(rx_dma, ENABLE);
|
|
|
}
|
|
|
-
|
|
|
- uartx->SR;
|
|
|
- uartx->DR;
|
|
|
- }
|
|
|
- else
|
|
|
- {
|
|
|
- uartx->SR;
|
|
|
- uartx->DR;
|
|
|
}
|
|
|
+
|
|
|
+ return ret;
|
|
|
}
|
|
|
|
|
|
-static void _uart_tx_dma_isr_callback(struct stm32_uart *uart)
|
|
|
+/* ========== UART接收数据(从fifo往外读) ========== */
|
|
|
+static uint32_t uart_rx_data(struct _uart_config *config, void *data, uint32_t len)
|
|
|
{
|
|
|
- DMA_Stream_TypeDef *tx_dma = uart->_config->_tx_dma;
|
|
|
- rkfifo_t *tx_fifo = &uart->_config->_tx_fifo;
|
|
|
- uint32_t tcif = uart->_config->_tx_dma_tcif;
|
|
|
- uint32_t teif = uart->_config->_tx_dma_teif;
|
|
|
-
|
|
|
- if (DMA_GetITStatus(tx_dma, tcif) == SET)
|
|
|
- {
|
|
|
- DMA_ClearITPendingBit(tx_dma, tcif);
|
|
|
- DMA_Cmd(tx_dma, DISABLE);
|
|
|
-
|
|
|
- // fifo 中是否还有数据, 如果还有数据, 则读取到 dma buff 中并进行发送
|
|
|
- uint8_t *dma_buff = uart->_config->_dma_tx_buff;
|
|
|
- uint32_t dma_buff_size = uart->_config->_dma_tx_buff_size;
|
|
|
- uint32_t count = rkfifo_out(tx_fifo, dma_buff, dma_buff_size);
|
|
|
- if (count > 0)
|
|
|
- {
|
|
|
- DMA_SetCurrDataCounter(tx_dma, count);
|
|
|
- DMA_Cmd(tx_dma, ENABLE);
|
|
|
- }
|
|
|
- else
|
|
|
- {
|
|
|
- // 数据发送完成,在多线程时可以抛出信号量
|
|
|
- }
|
|
|
- }
|
|
|
- else if (DMA_GetITStatus(tx_dma, teif) == SET)
|
|
|
- {
|
|
|
- DMA_ClearITPendingBit(tx_dma, teif);
|
|
|
- }
|
|
|
+ return rkfifo_out(&config->rx_fifo, data, len);
|
|
|
}
|
|
|
|
|
|
-static void _uart_rx_dma_isr_callback(struct stm32_uart *uart)
|
|
|
+/* ========== UART中断处理函数 ========== */
|
|
|
+void uart_isr_callback(struct _uart_config *config)
|
|
|
{
|
|
|
- DMA_Stream_TypeDef *rx_dma = uart->_config->_rx_dma;
|
|
|
- rkfifo_t *rx_fifo = &uart->_config->_rx_fifo;
|
|
|
- uint32_t tcif = uart->_config->_rx_dma_tcif;
|
|
|
- uint32_t teif = uart->_config->_rx_dma_teif;
|
|
|
-
|
|
|
- if (DMA_GetITStatus(rx_dma, tcif) == SET)
|
|
|
- {
|
|
|
- DMA_ClearITPendingBit(rx_dma, tcif);
|
|
|
- DMA_Cmd(rx_dma, DISABLE);
|
|
|
-
|
|
|
- uint8_t *dma_buff = uart->_config->_dma_rx_buff;
|
|
|
- uint32_t dma_buff_size = uart->_config->_dma_rx_buff_size;
|
|
|
-
|
|
|
- uint32_t dma_cnt = dma_buff_size - DMA_GetCurrDataCounter(rx_dma);
|
|
|
- if (dma_cnt)
|
|
|
- {
|
|
|
- rkfifo_in(rx_fifo, &dma_buff[0], dma_cnt);
|
|
|
+ uint8_t count = 0;
|
|
|
+ rkfifo_t *rxfifo = &config->rx_fifo;
|
|
|
+ uint8_t irq_id = uart_get_irq_id(config->uart_base);
|
|
|
+
|
|
|
+ if (irq_id == uart_intr_id_rx_data_avail) {
|
|
|
+ while (uart_check_status(config->uart_base, uart_stat_data_ready)) {
|
|
|
+ uint8_t byte = uart_read_byte(config->uart_base);
|
|
|
+ rkfifo_in(rxfifo, &byte, 1);
|
|
|
+ count++;
|
|
|
+ /* 确保RX FIFO不会溢出 */
|
|
|
+ if (count > 12) {
|
|
|
+ break;
|
|
|
+ }
|
|
|
}
|
|
|
- //重新设置传输数据长度
|
|
|
- DMA_SetCurrDataCounter(rx_dma, dma_buff_size);
|
|
|
- //打开DMA
|
|
|
- DMA_Cmd(rx_dma, ENABLE);
|
|
|
}
|
|
|
- else if (DMA_GetITStatus(rx_dma, teif) == SET)
|
|
|
- {
|
|
|
- DMA_ClearITPendingBit(rx_dma, teif);
|
|
|
+
|
|
|
+ if (irq_id == uart_intr_id_rx_timeout) {
|
|
|
+ /* 接收超时,读取剩余数据 */
|
|
|
+ while (uart_check_status(config->uart_base, uart_stat_data_ready)) {
|
|
|
+ uint8_t byte = uart_read_byte(config->uart_base);
|
|
|
+ rkfifo_in(rxfifo, &byte, 1);
|
|
|
+ }
|
|
|
}
|
|
|
}
|
|
|
-/**--------------------------- UART1 -----------------------------------------*/
|
|
|
-#ifdef DRV_USING_UART1
|
|
|
-static uint8_t u1_rx_fifo_buff[UART1_RX_FIFO_BUFFER_LEN] = {0};
|
|
|
-static uint8_t u1_tx_fifo_buff[UART1_TX_FIFO_BUFFER_LEN] = {0};
|
|
|
-#ifdef UART1_TX_USING_DMA
|
|
|
-static uint8_t usart1_dma_tx_buf[UART1_TX_DMA_BUFFER_LEN] = {0};
|
|
|
-#endif
|
|
|
-#ifdef UART1_RX_USING_DMA
|
|
|
-static uint8_t usart1_dma_rx_buf[UART1_RX_DMA_BUFFER_LEN] = {0};
|
|
|
-#endif
|
|
|
-
|
|
|
-struct stm32_uart_config _u1_config = {
|
|
|
- .uartx = USART1,
|
|
|
- ._tx_port = GPIOA,
|
|
|
- ._tx_pin = GPIO_Pin_9,
|
|
|
- ._rx_port = GPIOA,
|
|
|
- ._rx_pin = GPIO_Pin_10,
|
|
|
- ._uart_irq_channel = USART1_IRQn,
|
|
|
-
|
|
|
- ._tx_fifo_buff = u1_tx_fifo_buff,
|
|
|
- ._tx_fifo_buff_size = sizeof(u1_tx_fifo_buff),
|
|
|
- ._rx_fifo_buff = u1_rx_fifo_buff,
|
|
|
- ._rx_fifo_buff_size = sizeof(u1_rx_fifo_buff),
|
|
|
-
|
|
|
-#ifdef UART1_RX_USING_DMA
|
|
|
- ._rx_dma = DMA2_Stream2,
|
|
|
- ._rx_dma_tcif = DMA_IT_TCIF2,
|
|
|
- ._rx_dma_teif = DMA_IT_TEIF2,
|
|
|
- ._rx_dma_channel = DMA_Channel_4,
|
|
|
- ._dma_rx_buff = usart1_dma_rx_buf,
|
|
|
- ._dma_rx_buff_size = sizeof(usart1_dma_rx_buf),
|
|
|
- ._rx_dma_irq_channel = DMA2_Stream2_IRQn,
|
|
|
-#else
|
|
|
- ._rx_dma = NULL,
|
|
|
-#endif // USART1_RX_USING_DMA
|
|
|
-
|
|
|
-#ifdef UART1_TX_USING_DMA
|
|
|
- ._tx_dma = DMA2_Stream7,
|
|
|
- ._tx_dma_tcif = DMA_IT_TCIF7,
|
|
|
- ._tx_dma_teif = DMA_IT_TEIF7,
|
|
|
- ._tx_dma_channel = DMA_Channel_4,
|
|
|
- ._dma_tx_buff = usart1_dma_tx_buf,
|
|
|
- ._dma_tx_buff_size = sizeof(usart1_dma_tx_buf),
|
|
|
- ._tx_dma_irq_channel = DMA2_Stream7_IRQn,
|
|
|
-#else
|
|
|
- ._tx_dma = NULL,
|
|
|
-#endif // USART1_TX_USING_DMA
|
|
|
-};
|
|
|
-
|
|
|
-static uint32_t u1_write_data(const void *pdata, uint32_t len)
|
|
|
-{
|
|
|
- return uart_tx_data(&_u1_config, pdata, len);
|
|
|
-}
|
|
|
-static uint32_t u1_read_data(void *pdata, uint32_t len)
|
|
|
-{
|
|
|
- return uart_rx_data(&_u1_config, pdata, len);
|
|
|
-}
|
|
|
-static int u1_init(uint32_t bps)
|
|
|
-{
|
|
|
- return uart_init(&_u1_config, bps);
|
|
|
-}
|
|
|
-
|
|
|
-static struct stm32_uart_ops _u1_ops = {
|
|
|
- .init = u1_init,
|
|
|
- .read = u1_read_data,
|
|
|
- .write = u1_write_data};
|
|
|
-
|
|
|
-static struct stm32_uart uart1 = {
|
|
|
- ._config = &_u1_config,
|
|
|
- .ops = &_u1_ops};
|
|
|
-
|
|
|
-void USART1_IRQHandler(void)
|
|
|
-{
|
|
|
- _uart_isr_callback(&uart1);
|
|
|
-}
|
|
|
|
|
|
-#ifdef UART1_TX_USING_DMA
|
|
|
-void DMA2_Stream7_IRQHandler(void)
|
|
|
+/* ========== DMA发送完成中断处理 ========== */
|
|
|
+void uart_tx_dma_isr_callback(struct _uart_config *config)
|
|
|
{
|
|
|
- _uart_tx_dma_isr_callback(&uart1);
|
|
|
+ bool *dma_done_flag = _get_dma_done_flag(config->uart_base);
|
|
|
+
|
|
|
+ /* 设置DMA完成标志 */
|
|
|
+ if (dma_done_flag) {
|
|
|
+ *dma_done_flag = true;
|
|
|
+ }
|
|
|
+
|
|
|
+ config->dma_busy = 0;
|
|
|
+
|
|
|
+ rkfifo_t *tx_fifo = &config->tx_fifo;
|
|
|
+ uint8_t *dma_buff = config->dma_tx_buff;
|
|
|
+ uint32_t dma_buff_size = config->dma_tx_buff_size;
|
|
|
+ uint32_t count = rkfifo_out(tx_fifo, dma_buff, dma_buff_size);
|
|
|
+
|
|
|
+ if (count > 0) {
|
|
|
+ open_usart_dma_tx(config, count);
|
|
|
+ config->dma_busy = 1;
|
|
|
+ }
|
|
|
}
|
|
|
-#endif
|
|
|
|
|
|
-#ifdef UART1_RX_USING_DMA
|
|
|
-void DMA2_Stream2_IRQHandler(void)
|
|
|
-{
|
|
|
- _uart_rx_dma_isr_callback(&uart1);
|
|
|
-}
|
|
|
-#endif
|
|
|
-#endif // DRV_USING_UART1
|
|
|
-
|
|
|
-/**--------------------------- UART2 -----------------------------------------*/
|
|
|
-#ifdef DRV_USING_UART2
|
|
|
-static uint8_t u2_rx_fifo_buff[UART2_RX_FIFO_BUFFER_LEN] = {0};
|
|
|
-static uint8_t u2_tx_fifo_buff[UART2_TX_FIFO_BUFFER_LEN] = {0};
|
|
|
-#ifdef UART2_TX_USING_DMA
|
|
|
-static uint8_t usart2_dma_tx_buf[UART2_TX_DMA_BUFFER_LEN] = {0};
|
|
|
-#endif
|
|
|
-#ifdef UART2_RX_USING_DMA
|
|
|
-static uint8_t usart2_dma_rx_buf[UART2_RX_DMA_BUFFER_LEN] = {0};
|
|
|
-#endif
|
|
|
+/* ========== UART1 配置 ========== */
|
|
|
+#ifdef DRV_USING_UART1
|
|
|
|
|
|
-struct stm32_uart_config _u2_config = {
|
|
|
- .uartx = USART2,
|
|
|
- ._tx_port = GPIOA,
|
|
|
- ._tx_pin = GPIO_Pin_2,
|
|
|
- ._rx_port = GPIOA,
|
|
|
- ._rx_pin = GPIO_Pin_3,
|
|
|
- ._uart_irq_channel = USART2_IRQn,
|
|
|
-
|
|
|
- ._tx_fifo_buff = u2_tx_fifo_buff,
|
|
|
- ._tx_fifo_buff_size = sizeof(u2_tx_fifo_buff),
|
|
|
- ._rx_fifo_buff = u2_rx_fifo_buff,
|
|
|
- ._rx_fifo_buff_size = sizeof(u2_rx_fifo_buff),
|
|
|
-
|
|
|
-#ifdef UART2_RX_USING_DMA
|
|
|
- ._rx_dma = DMA1_Stream5,
|
|
|
- ._rx_dma_tcif = DMA_IT_TCIF5,
|
|
|
- ._rx_dma_teif = DMA_IT_TEIF5,
|
|
|
- ._rx_dma_channel = DMA_Channel_4,
|
|
|
- ._dma_rx_buff = usart2_dma_rx_buf,
|
|
|
- ._dma_rx_buff_size = sizeof(usart2_dma_rx_buf),
|
|
|
- ._rx_dma_irq_channel = DMA1_Stream5_IRQn,
|
|
|
-#else
|
|
|
- ._rx_dma = NULL,
|
|
|
-#endif // USART1_RX_USING_DMA
|
|
|
-
|
|
|
-#ifdef UART2_TX_USING_DMA
|
|
|
- ._tx_dma = DMA1_Stream6,
|
|
|
- ._tx_dma_tcif = DMA_IT_TCIF6,
|
|
|
- ._tx_dma_teif = DMA_IT_TEIF6,
|
|
|
- ._tx_dma_channel = DMA_Channel_4,
|
|
|
- ._dma_tx_buff = usart2_dma_tx_buf,
|
|
|
- ._dma_tx_buff_size = sizeof(usart2_dma_tx_buf),
|
|
|
- ._tx_dma_irq_channel = DMA1_Stream6_IRQn,
|
|
|
-#else
|
|
|
- ._tx_dma = NULL,
|
|
|
-#endif // USART2_TX_USING_DMA
|
|
|
+static uint8_t u1_rx_fifo_buff[UART_RX_FIFO_BUFFER_LEN];
|
|
|
+static uint8_t u1_tx_fifo_buff[UART_TX_FIFO_BUFFER_LEN];
|
|
|
+static uint8_t u1_dma_tx_buff[UART_TX_DMA_BUFFER_LEN];
|
|
|
+
|
|
|
+struct _uart_config _u1_config = {
|
|
|
+ .uart_base = HPM_UART1, /* 修正:应该是UART1 */
|
|
|
+ .uart_irq_mask = uart_intr_rx_rdy | uart_intr_rx_timeout, /* 添加中断掩码 */
|
|
|
+ .uart_irq_num = IRQn_UART1, /* 修正:IRQn_UART1 */
|
|
|
+
|
|
|
+ /* DMA配置 */
|
|
|
+ .dma_base = HPM_DMA0,
|
|
|
+ .dma_mux_base = HPM_DMAMUX0,
|
|
|
+ .dma_enable = 1, /* 修正拼写 */
|
|
|
+ .dma_channel = 0,
|
|
|
+ .dma_irq_num = IRQn_DMA0_CH0,
|
|
|
+ .dma_request = DMA_REQUEST_UART1_TX, /* 修正:UART1_TX */
|
|
|
+
|
|
|
+ /* FIFO缓冲区 */
|
|
|
+ .tx_fifo_buff = u1_tx_fifo_buff,
|
|
|
+ .tx_fifo_buff_size = sizeof(u1_tx_fifo_buff),
|
|
|
+ .rx_fifo_buff = u1_rx_fifo_buff,
|
|
|
+ .rx_fifo_buff_size = sizeof(u1_rx_fifo_buff),
|
|
|
+
|
|
|
+ /* DMA缓冲区 */
|
|
|
+ .dma_tx_buff = u1_dma_tx_buff,
|
|
|
+ .dma_tx_buff_size = sizeof(u1_dma_tx_buff),
|
|
|
};
|
|
|
|
|
|
-static uint32_t u2_write_data(const void *pdata, uint32_t len)
|
|
|
-{
|
|
|
- return uart_tx_data(&_u2_config, pdata, len);
|
|
|
-}
|
|
|
-static uint32_t u2_read_data(void *pdata, uint32_t len)
|
|
|
-{
|
|
|
- return uart_rx_data(&_u2_config, pdata, len);
|
|
|
-}
|
|
|
-static int u2_init(uint32_t bps)
|
|
|
-{
|
|
|
- return uart_init(&_u2_config, bps);
|
|
|
-}
|
|
|
-
|
|
|
-static struct stm32_uart_ops _u2_ops = {
|
|
|
- .init = u2_init,
|
|
|
- .read = u2_read_data,
|
|
|
- .write = u2_write_data};
|
|
|
-
|
|
|
-static struct stm32_uart uart2 = {
|
|
|
- ._config = &_u2_config,
|
|
|
- .ops = &_u2_ops};
|
|
|
-
|
|
|
-void USART2_IRQHandler(void)
|
|
|
+static uint32_t u1_write_data(const void *data, uint32_t len)
|
|
|
{
|
|
|
- _uart_isr_callback(&uart2);
|
|
|
+ return uart_tx_data(&_u1_config, data, len);
|
|
|
}
|
|
|
|
|
|
-#ifdef UART2_TX_USING_DMA
|
|
|
-void DMA1_Stream6_IRQHandler(void)
|
|
|
+static uint32_t u1_read_data(void *data, uint32_t len)
|
|
|
{
|
|
|
- _uart_tx_dma_isr_callback(&uart1);
|
|
|
+ return uart_rx_data(&_u1_config, data, len);
|
|
|
}
|
|
|
-#endif
|
|
|
|
|
|
-#ifdef UART2_RX_USING_DMA
|
|
|
-void DMA1_Stream5_IRQHandler(void)
|
|
|
+static int u1_init(uint32_t baudrate)
|
|
|
{
|
|
|
- _uart_rx_dma_isr_callback(&uart1);
|
|
|
+ return _uart_init(&_u1_config, baudrate);
|
|
|
}
|
|
|
-#endif
|
|
|
-#endif // DRV_USING_UART2
|
|
|
-
|
|
|
-/**--------------------------- UART3 -----------------------------------------*/
|
|
|
-
|
|
|
-
|
|
|
-/**--------------------------- UART4 -----------------------------------------*/
|
|
|
-#ifdef DRV_USING_UART4
|
|
|
-static uint8_t u4_rx_fifo_buff[UART4_RX_FIFO_BUFFER_LEN] = {0};
|
|
|
-static uint8_t u4_tx_fifo_buff[UART4_TX_FIFO_BUFFER_LEN] = {0};
|
|
|
-#ifdef UART4_TX_USING_DMA
|
|
|
-static uint8_t u4_dma_tx_buf[UART4_TX_DMA_BUFFER_LEN] = {0};
|
|
|
-#endif
|
|
|
-#ifdef UART4_RX_USING_DMA
|
|
|
-static uint8_t u4_dma_rx_buf[UART4_RX_DMA_BUFFER_LEN] = {0};
|
|
|
-#endif
|
|
|
-
|
|
|
-struct stm32_uart_config _u4_config = {
|
|
|
- .uartx = UART4,
|
|
|
- ._tx_port = GPIOA,
|
|
|
- ._tx_pin = GPIO_Pin_0,
|
|
|
- ._rx_port = GPIOA,
|
|
|
- ._rx_pin = GPIO_Pin_1,
|
|
|
- ._uart_irq_channel = UART4_IRQn,
|
|
|
-
|
|
|
- ._tx_fifo_buff = u4_tx_fifo_buff,
|
|
|
- ._tx_fifo_buff_size = sizeof(u4_tx_fifo_buff),
|
|
|
- ._rx_fifo_buff = u4_rx_fifo_buff,
|
|
|
- ._rx_fifo_buff_size = sizeof(u4_rx_fifo_buff),
|
|
|
-
|
|
|
-#ifdef UART4_RX_USING_DMA
|
|
|
- ._rx_dma = DMA1_Stream2,
|
|
|
- ._rx_dma_tcif = DMA_IT_TCIF2,
|
|
|
- ._rx_dma_teif = DMA_IT_TEIF2,
|
|
|
- ._rx_dma_channel = DMA_Channel_4,
|
|
|
- ._dma_rx_buff = u4_dma_rx_buf,
|
|
|
- ._dma_rx_buff_size = sizeof(u4_dma_rx_buf),
|
|
|
- ._rx_dma_irq_channel = DMA1_Stream2_IRQn,
|
|
|
-#else
|
|
|
- ._rx_dma = NULL,
|
|
|
-#endif
|
|
|
|
|
|
-#ifdef UART4_TX_USING_DMA
|
|
|
- ._tx_dma = DMA1_Stream4,
|
|
|
- ._tx_dma_tcif = DMA_IT_TCIF4,
|
|
|
- ._tx_dma_teif = DMA_IT_TEIF4,
|
|
|
- ._tx_dma_channel = DMA_Channel_4,
|
|
|
- ._dma_tx_buff = u4_dma_tx_buf,
|
|
|
- ._dma_tx_buff_size = sizeof(u4_dma_tx_buf),
|
|
|
- ._tx_dma_irq_channel = DMA1_Stream4_IRQn,
|
|
|
-#else
|
|
|
- ._tx_dma = NULL,
|
|
|
-#endif
|
|
|
+static struct _uart_ops _u1_ops = {
|
|
|
+ .init = u1_init,
|
|
|
+ .read = u1_read_data,
|
|
|
+ .write = u1_write_data,
|
|
|
};
|
|
|
|
|
|
-static uint32_t u4_write_data(const void *pdata, uint32_t len)
|
|
|
-{
|
|
|
- return uart_tx_data(&_u4_config, pdata, len);
|
|
|
-}
|
|
|
-static uint32_t u4_read_data(void *pdata, uint32_t len)
|
|
|
-{
|
|
|
- return uart_rx_data(&_u4_config, pdata, len);
|
|
|
-}
|
|
|
-static int u4_init(uint32_t bps)
|
|
|
-{
|
|
|
- return uart_init(&_u4_config, bps);
|
|
|
-}
|
|
|
-
|
|
|
-static struct stm32_uart_ops _u4_ops = {
|
|
|
- .init = u4_init,
|
|
|
- .read = u4_read_data,
|
|
|
- .write = u4_write_data};
|
|
|
-
|
|
|
-static struct stm32_uart uart4 = {
|
|
|
- ._config = &_u4_config,
|
|
|
- .ops = &_u4_ops};
|
|
|
+static struct _uart_device uart1 = {
|
|
|
+ .config = &_u1_config,
|
|
|
+ .ops = &_u1_ops,
|
|
|
+};
|
|
|
|
|
|
-void UART4_IRQHandler(void)
|
|
|
+/* UART1中断处理函数 */
|
|
|
+void uart1_irq_handler(void)
|
|
|
{
|
|
|
- _uart_isr_callback(&uart4);
|
|
|
+ uart_isr_callback(&_u1_config);
|
|
|
}
|
|
|
|
|
|
-#ifdef UART4_RX_USING_DMA
|
|
|
-void DMA1_Stream2_IRQHandler(void)
|
|
|
+/* DMA0通道0中断处理函数 */
|
|
|
+void dma0_ch0_irq_handler(void)
|
|
|
{
|
|
|
- _uart_rx_dma_isr_callback(&uart4);
|
|
|
+ uart_tx_dma_isr_callback(&_u1_config);
|
|
|
}
|
|
|
-#endif
|
|
|
|
|
|
-#ifdef UART4_TX_USING_DMA
|
|
|
-void DMA1_Stream4_IRQHandler(void)
|
|
|
-{
|
|
|
- _uart_tx_dma_isr_callback(&uart4);
|
|
|
-}
|
|
|
-#endif
|
|
|
-#endif // DRV_USING_UART4
|
|
|
+#endif /* DRV_USING_UART1 */
|
|
|
|
|
|
-struct stm32_uart *uart_find(const char *name)
|
|
|
+/* ========== UART查找函数 ========== */
|
|
|
+struct _uart_device *uart_find(const char *name)
|
|
|
{
|
|
|
- struct stm32_uart *uart = NULL;
|
|
|
- if (strncmp(name, "uart1", 5) == 0)
|
|
|
- {
|
|
|
+ struct _uart_device *uart = NULL;
|
|
|
+
|
|
|
+ if (strncmp(name, "uart1", 5) == 0) {
|
|
|
#ifdef DRV_USING_UART1
|
|
|
uart = &uart1;
|
|
|
-#endif // DEBUG
|
|
|
- }
|
|
|
- else if (strncmp(name, "uart2", 5) == 0)
|
|
|
- {
|
|
|
+#endif
|
|
|
+ } else if (strncmp(name, "uart2", 5) == 0) {
|
|
|
#ifdef DRV_USING_UART2
|
|
|
uart = &uart2;
|
|
|
-#endif // DEBUG
|
|
|
- }
|
|
|
- else if (strncmp(name, "uart3", 5) == 0)
|
|
|
- {
|
|
|
+#endif
|
|
|
+ } else if (strncmp(name, "uart3", 5) == 0) {
|
|
|
#ifdef DRV_USING_UART3
|
|
|
uart = &uart3;
|
|
|
-#endif // DEBUG
|
|
|
- }
|
|
|
- else if (strncmp(name, "uart4", 5) == 0)
|
|
|
- {
|
|
|
+#endif
|
|
|
+ } else if (strncmp(name, "uart4", 5) == 0) {
|
|
|
#ifdef DRV_USING_UART4
|
|
|
uart = &uart4;
|
|
|
-#endif // DEBUG
|
|
|
- }
|
|
|
- else if (strncmp(name, "uart5", 5) == 0)
|
|
|
- {
|
|
|
+#endif
|
|
|
+ } else if (strncmp(name, "uart5", 5) == 0) {
|
|
|
#ifdef DRV_USING_UART5
|
|
|
uart = &uart5;
|
|
|
-#endif // DEBUG
|
|
|
- }
|
|
|
- else if (strncmp(name, "uart6", 5) == 0)
|
|
|
- {
|
|
|
+#endif
|
|
|
+ } else if (strncmp(name, "uart6", 5) == 0) {
|
|
|
#ifdef DRV_USING_UART6
|
|
|
uart = &uart6;
|
|
|
-#endif // DEBUG
|
|
|
- }
|
|
|
- else
|
|
|
- {
|
|
|
- uart = NULL;
|
|
|
+#endif
|
|
|
}
|
|
|
-
|
|
|
+
|
|
|
return uart;
|
|
|
-}
|
|
|
+}
|