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@@ -0,0 +1,918 @@
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+#include "drv_usart.h"
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+#include "rkfifo.h"
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+#include "stm32f4xx.h"
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+#include "string.h"
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+#include "board.h"
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+
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+
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+static inline int _stm32_uart_rcc_enable(USART_TypeDef *uartx)
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+{
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+ int ret = 0;
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+ switch ((uint32_t)uartx)
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+ {
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+ case (uint32_t)USART1:
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+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
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+ break;
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+ case (uint32_t)USART2:
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+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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+ break;
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+ case (uint32_t)USART3:
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+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
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+ break;
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+ case (uint32_t)UART4:
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+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
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+ break;
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+ case (uint32_t)UART5:
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+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
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+ break;
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+ case (uint32_t)USART6:
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+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
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+ break;
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+
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+ default:
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+ ret = -1;
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+ break;
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+ }
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+ return ret;
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+}
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+
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+static inline int _stm32_dma_rcc_enable(DMA_Stream_TypeDef *tx_dma)
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+{
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+ int ret = 0;
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+ switch ((uint32_t)tx_dma)
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+ {
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+ case (uint32_t)DMA1_Stream0:
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+ case (uint32_t)DMA1_Stream1:
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+ case (uint32_t)DMA1_Stream2:
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+ case (uint32_t)DMA1_Stream3:
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+ case (uint32_t)DMA1_Stream4:
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+ case (uint32_t)DMA1_Stream5:
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+ case (uint32_t)DMA1_Stream6:
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+ case (uint32_t)DMA1_Stream7:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
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+ break;
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+
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+ case (uint32_t)DMA2_Stream0:
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+ case (uint32_t)DMA2_Stream1:
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+ case (uint32_t)DMA2_Stream2:
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+ case (uint32_t)DMA2_Stream3:
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+ case (uint32_t)DMA2_Stream4:
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+ case (uint32_t)DMA2_Stream5:
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+ case (uint32_t)DMA2_Stream6:
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+ case (uint32_t)DMA2_Stream7:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
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+ break;
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+
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+ default:
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+ ret = -1;
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+static inline int _stm32_gpio_rcc_enable(GPIO_TypeDef *port)
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+{
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+ int ret = 0;
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+ switch ((uint32_t)port)
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+ {
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+ case (uint32_t)GPIOA:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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+ break;
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+ case (uint32_t)GPIOB:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
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+ break;
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+ case (uint32_t)GPIOC:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
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+ break;
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+ case (uint32_t)GPIOD:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
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+ break;
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+ case (uint32_t)GPIOE:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE);
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+ break;
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+ case (uint32_t)GPIOF:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE);
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+ break;
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+ case (uint32_t)GPIOG:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE);
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+ break;
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+ case (uint32_t)GPIOH:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOH, ENABLE);
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+ break;
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+ case (uint32_t)GPIOI:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOI, ENABLE);
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+ break;
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+ case (uint32_t)GPIOJ:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
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+ break;
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+ case (uint32_t)GPIOK:
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+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOK, ENABLE);
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+ break;
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+ default:
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+ ret = -1;
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+ break;
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+ }
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+ return ret;
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+}
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+
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+static inline uint16_t _stm32_get_pinaf(uint16_t pin)
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+{
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+ uint16_t ret = 0xff;
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+ switch (pin)
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+ {
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+ case GPIO_Pin_0:
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+ ret = GPIO_PinSource0;
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+ break;
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+ case GPIO_Pin_1:
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+ ret = GPIO_PinSource1;
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+ break;
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+ case GPIO_Pin_2:
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+ ret = GPIO_PinSource2;
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+ break;
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+ case GPIO_Pin_3:
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+ ret = GPIO_PinSource3;
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+ break;
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+ case GPIO_Pin_4:
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+ ret = GPIO_PinSource4;
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+ break;
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+ case GPIO_Pin_5:
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+ ret = GPIO_PinSource5;
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+ break;
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+ case GPIO_Pin_6:
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+ ret = GPIO_PinSource6;
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+ break;
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+ case GPIO_Pin_7:
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+ ret = GPIO_PinSource7;
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+ break;
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+ case GPIO_Pin_8:
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+ ret = GPIO_PinSource8;
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+ break;
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+ case GPIO_Pin_9:
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+ ret = GPIO_PinSource9;
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+ break;
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+ case GPIO_Pin_10:
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+ ret = GPIO_PinSource10;
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+ break;
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+ case GPIO_Pin_11:
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+ ret = GPIO_PinSource11;
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+ break;
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+ case GPIO_Pin_12:
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+ ret = GPIO_PinSource12;
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+ break;
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+ case GPIO_Pin_13:
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+ ret = GPIO_PinSource13;
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+ break;
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+ case GPIO_Pin_14:
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+ ret = GPIO_PinSource14;
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+ break;
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+ case GPIO_Pin_15:
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+ ret = GPIO_PinSource15;
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+ break;
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+ default:
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+ break;
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+ }
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+ return ret;
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+}
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+
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+static inline uint8_t _stm32_get_uartaf(USART_TypeDef *uartx)
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+{
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+ uint8_t ret = 0;
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+ switch ((uint32_t)uartx)
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+ {
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+ case (uint32_t)USART1:
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+ ret = GPIO_AF_USART1;
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+ break;
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+ case (uint32_t)USART2:
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+ ret = GPIO_AF_USART2;
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+ break;
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+ case (uint32_t)USART3:
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+ ret = GPIO_AF_USART3;
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+ break;
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+ case (uint32_t)UART4:
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+ ret = GPIO_AF_UART4;
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+ break;
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+ case (uint32_t)UART5:
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+ ret = GPIO_AF_UART5;
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+ break;
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+ case (uint32_t)USART6:
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+ ret = GPIO_AF_USART6;
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+ break;
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+
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+ default:
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+ ret = -1;
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+ break;
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+ }
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+ return ret;
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+}
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+
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+static int _uart_config(struct stm32_uart_config *uart, uint32_t bps)
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+{
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+ int ret = 0;
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+ _stm32_uart_rcc_enable(uart->uartx);
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+ _stm32_gpio_rcc_enable(uart->_tx_port);
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+ _stm32_gpio_rcc_enable(uart->_rx_port);
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+
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+ USART_DeInit(uart->uartx);
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+ GPIO_InitTypeDef GPIO_InitStructure;
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+ GPIO_StructInit(&GPIO_InitStructure);
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+ GPIO_InitStructure.GPIO_Pin = uart->_tx_pin;
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+ GPIO_InitStructure.GPIO_Speed = GPIO_High_Speed;
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+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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+ GPIO_Init(uart->_tx_port, &GPIO_InitStructure);
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+ GPIO_InitStructure.GPIO_Pin = uart->_rx_pin;
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+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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+ GPIO_Init(uart->_rx_port, &GPIO_InitStructure);
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+
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+ GPIO_PinAFConfig(uart->_rx_port, _stm32_get_pinaf(uart->_rx_pin), _stm32_get_uartaf(uart->uartx));
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+ GPIO_PinAFConfig(uart->_tx_port, _stm32_get_pinaf(uart->_tx_pin), _stm32_get_uartaf(uart->uartx));
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+
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+ USART_InitTypeDef USART_InitStructure;
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+ USART_StructInit(&USART_InitStructure);
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+ USART_InitStructure.USART_BaudRate = bps;
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+
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+ USART_Init(uart->uartx, &USART_InitStructure);
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+
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+ if (uart->_rx_dma == NULL)
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+ {
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+ /* 采用中断式接收 */
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+ USART_ITConfig(uart->uartx, USART_IT_RXNE, ENABLE);
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+ }
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+ else
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+ {
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+ /* 采用 dma 式接收*/
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+ USART_ITConfig(uart->uartx, USART_IT_IDLE, ENABLE);
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+ }
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+
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+ USART_Cmd(uart->uartx, ENABLE);
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+
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+ return ret;
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+}
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+
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+static int _uart_dma_config(struct stm32_uart_config *uart)
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+{
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+ int ret = 0;
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+ DMA_InitTypeDef dma_conf;
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+
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+ /* tx dma config */
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+ if (uart->_tx_dma && uart->_dma_tx_buff)
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+ {
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+ _stm32_dma_rcc_enable(uart->_tx_dma);
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+ DMA_DeInit(uart->_tx_dma);
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+ while (DMA_GetCmdStatus(uart->_tx_dma) != DISABLE)
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+ {
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+ };
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+ DMA_StructInit(&dma_conf);
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+ dma_conf.DMA_Channel = uart->_tx_dma_channel;
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+ dma_conf.DMA_PeripheralBaseAddr = (u32)(&(uart->uartx->DR));
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+ dma_conf.DMA_Memory0BaseAddr = (u32)uart->_dma_tx_buff;
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+ dma_conf.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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+ dma_conf.DMA_BufferSize = (uint32_t)uart->_dma_tx_buff;
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+ dma_conf.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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+ dma_conf.DMA_MemoryInc = DMA_MemoryInc_Enable;
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+ dma_conf.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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+ dma_conf.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
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+ dma_conf.DMA_Mode = DMA_Mode_Normal;
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+ dma_conf.DMA_Priority = DMA_Priority_Medium;
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+ dma_conf.DMA_FIFOMode = DMA_FIFOMode_Disable;
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+ dma_conf.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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+ dma_conf.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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+ dma_conf.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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+ DMA_Init(uart->_tx_dma, &dma_conf);
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+ DMA_ITConfig(uart->_tx_dma, DMA_IT_TC, ENABLE);
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+ DMA_ITConfig(uart->_tx_dma, DMA_IT_TE, ENABLE);
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+ DMA_Cmd(uart->_tx_dma, DISABLE);
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+ // 串口采用 dma 发送
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+ USART_DMACmd(uart->uartx, USART_DMAReq_Tx, ENABLE);
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+ //等待关闭使能完成
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+ while (DMA_GetCmdStatus(uart->_tx_dma) != DISABLE)
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+ {
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+ };
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+ }
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+
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+ /* rx dma config */
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+ if (uart->_rx_dma && uart->_dma_rx_buff)
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+ {
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+ // 配置串口的 dma 接收
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+ _stm32_dma_rcc_enable(uart->_rx_dma);
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+ DMA_StructInit(&dma_conf);
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+ DMA_DeInit(uart->_rx_dma);
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+ while (DMA_GetCmdStatus(uart->_rx_dma) != DISABLE)
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+ {
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+ };
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+ dma_conf.DMA_Channel = uart->_rx_dma_channel;
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+ dma_conf.DMA_PeripheralBaseAddr = (u32)(&uart->uartx->DR);
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+ dma_conf.DMA_Memory0BaseAddr = (u32)uart->_dma_rx_buff;
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+ dma_conf.DMA_DIR = DMA_DIR_PeripheralToMemory;
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+ dma_conf.DMA_BufferSize = uart->_dma_rx_buff_size;
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+ dma_conf.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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+ dma_conf.DMA_MemoryInc = DMA_MemoryInc_Enable;
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+ dma_conf.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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+ dma_conf.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
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+ dma_conf.DMA_Mode = DMA_Mode_Normal;
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+ dma_conf.DMA_Priority = DMA_Priority_High;
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+ dma_conf.DMA_FIFOMode = DMA_FIFOMode_Disable;
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+ dma_conf.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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+ dma_conf.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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+ dma_conf.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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+ DMA_Init(uart->_rx_dma, &dma_conf);
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+ DMA_ITConfig(uart->_rx_dma, DMA_IT_TC, ENABLE);
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+ DMA_ITConfig(uart->_rx_dma, DMA_IT_TE, ENABLE);
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+ DMA_Cmd(uart->_rx_dma, ENABLE);
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+ /* 串口采用 dma 接收 */
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+ USART_DMACmd(uart->uartx, USART_DMAReq_Rx, ENABLE);
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+ while (DMA_GetCmdStatus(uart->_rx_dma) != ENABLE)
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+ {
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+ };
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+ }
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+
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+ return ret;
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+}
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+
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+void _uart_nvic_config(struct stm32_uart_config *uart)
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+{
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+ NVIC_InitTypeDef NVIC_InitStructure;
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+
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+ NVIC_InitStructure.NVIC_IRQChannel = uart->_uart_irq_channel;
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+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
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+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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+ NVIC_Init(&NVIC_InitStructure);
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+
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+ if (uart->_rx_dma && uart->_dma_rx_buff)
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+ {
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+ NVIC_InitStructure.NVIC_IRQChannel = uart->_rx_dma_irq_channel;
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+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
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+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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+ NVIC_Init(&NVIC_InitStructure);
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+ }
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+
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+ if (uart->_tx_dma && uart->_dma_tx_buff)
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+ {
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+ NVIC_InitStructure.NVIC_IRQChannel = uart->_tx_dma_irq_channel;
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+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
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+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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+ NVIC_Init(&NVIC_InitStructure);
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+ }
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+}
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+
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+int uart_init(struct stm32_uart_config *uart, uint32_t bps)
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+{
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+ int ret = 0;
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+ rkfifo_init(&uart->_rx_fifo, uart->_rx_fifo_buff, uart->_rx_fifo_buff_size, 1);
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+ rkfifo_init(&uart->_tx_fifo, uart->_tx_fifo_buff, uart->_tx_fifo_buff_size, 1);
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+
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+ _uart_config(uart, bps);
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+ _uart_dma_config(uart);
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+ _uart_nvic_config(uart);
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+
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+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief 串口发送数据
|
|
|
+ *
|
|
|
+ * @param uart 串口对象
|
|
|
+ * @param pdata 发送的数据指针
|
|
|
+ * @param len 发送的数据长度
|
|
|
+ * @return uint32_t 实际发送的数据长度
|
|
|
+ */
|
|
|
+static uint32_t uart_tx_data(struct stm32_uart_config *uart, const void *pdata, uint32_t len)
|
|
|
+{
|
|
|
+ assert_param(uart != NULL);
|
|
|
+ assert_param(pdata != NULL);
|
|
|
+ uint32_t ret = 0;
|
|
|
+ if (len > 0)
|
|
|
+ {
|
|
|
+ /* 将数据压入 tx FIFO */
|
|
|
+ ret = rkfifo_in(&uart->_tx_fifo, pdata, len);
|
|
|
+
|
|
|
+ if (uart->_tx_dma)
|
|
|
+ {
|
|
|
+ /* dma 形式发送数据 */
|
|
|
+ if ((USART_GetFlagStatus(uart->uartx, USART_FLAG_TXE) == SET) &&
|
|
|
+ (USART_GetFlagStatus(uart->uartx, USART_FLAG_TC) == SET))
|
|
|
+ {
|
|
|
+ // fifo 中是否还有数据, 如果还有数据, 则读取到 dma buff 中并进行发送
|
|
|
+ uint32_t count = rkfifo_out(&uart->_tx_fifo,
|
|
|
+ uart->_dma_tx_buff,
|
|
|
+ uart->_dma_tx_buff_size);
|
|
|
+ if (count > 0)
|
|
|
+ {
|
|
|
+ DMA_SetCurrDataCounter(uart->_tx_dma, count);
|
|
|
+ DMA_Cmd(uart->_tx_dma, ENABLE);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* 中断形式发送数据 */
|
|
|
+ USART_ITConfig(uart->uartx, USART_IT_TXE, ENABLE);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief 串口读取数据
|
|
|
+ *
|
|
|
+ * @param uart 串口对象
|
|
|
+ * @param pdata 数据读取输出 buffer
|
|
|
+ * @param len 数据读取长度
|
|
|
+ * @return uint32_t 实际读出的长度
|
|
|
+ */
|
|
|
+static uint32_t uart_rx_data(struct stm32_uart_config *uart, void *pdata, uint32_t len)
|
|
|
+{
|
|
|
+ assert_param(uart != NULL);
|
|
|
+ assert_param(pdata != NULL);
|
|
|
+
|
|
|
+ uint32_t ret = rkfifo_out(&uart->_rx_fifo, pdata, len);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void _rxne_isr_callback(struct stm32_uart *uart)
|
|
|
+{
|
|
|
+ assert_param(uart != NULL);
|
|
|
+
|
|
|
+ USART_TypeDef *uartx = uart->_config->uartx;
|
|
|
+ rkfifo_t *rxfifo = &uart->_config->_rx_fifo;
|
|
|
+
|
|
|
+ uint8_t data;
|
|
|
+ data = USART_ReceiveData(uartx) & 0xFF;
|
|
|
+ /* 将接收到的数据压入 fifo */
|
|
|
+ rkfifo_in(rxfifo, &data, 1);
|
|
|
+ USART_ClearITPendingBit(uartx, USART_IT_RXNE);
|
|
|
+}
|
|
|
+
|
|
|
+static void _txe_isr_callback(struct stm32_uart *uart)
|
|
|
+{
|
|
|
+ assert_param(uart != NULL);
|
|
|
+
|
|
|
+ USART_TypeDef *usartx = uart->_config->uartx;
|
|
|
+ rkfifo_t *txfifo = &uart->_config->_tx_fifo;
|
|
|
+
|
|
|
+ if (USART_GetITStatus(usartx, USART_IT_TXE) == SET)
|
|
|
+ {
|
|
|
+ uint8_t c;
|
|
|
+ if (rkfifo_out(txfifo, &c, 1))
|
|
|
+ {
|
|
|
+ /* fifo 有数据, 继续发送 */
|
|
|
+ USART_SendData(usartx, c);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* fifo 无数据, 关闭 txe 中断, 打开 TC 中断 */
|
|
|
+ USART_ITConfig(usartx, USART_IT_TXE, DISABLE);
|
|
|
+ USART_ITConfig(usartx, USART_IT_TC, ENABLE);
|
|
|
+ }
|
|
|
+
|
|
|
+ USART_ClearITPendingBit(usartx, USART_IT_TXE);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void _tc_isr_callback(struct stm32_uart *uart)
|
|
|
+{
|
|
|
+ assert_param(uart != NULL);
|
|
|
+
|
|
|
+ USART_TypeDef *usartx = uart->_config->uartx;
|
|
|
+
|
|
|
+ USART_ClearITPendingBit(usartx, USART_IT_TC);
|
|
|
+}
|
|
|
+
|
|
|
+static void _uart_isr_callback(struct stm32_uart *uart)
|
|
|
+{
|
|
|
+ USART_TypeDef *uartx = uart->_config->uartx;
|
|
|
+ DMA_Stream_TypeDef *rx_dma = uart->_config->_rx_dma;
|
|
|
+ uint8_t *rx_dma_buff = uart->_config->_dma_rx_buff;
|
|
|
+ uint32_t rx_dma_buff_size = uart->_config->_dma_rx_buff_size;
|
|
|
+ rkfifo_t *rx_fifo = &uart->_config->_rx_fifo;
|
|
|
+
|
|
|
+ if (USART_GetITStatus(uartx, USART_IT_RXNE) == SET)
|
|
|
+ {
|
|
|
+ _rxne_isr_callback(uart);
|
|
|
+ }
|
|
|
+ else if (USART_GetITStatus(uartx, USART_IT_TXE) == SET)
|
|
|
+ {
|
|
|
+ _txe_isr_callback(uart);
|
|
|
+ }
|
|
|
+ else if (USART_GetITStatus(uartx, USART_IT_TC) == SET)
|
|
|
+ {
|
|
|
+ _tc_isr_callback(uart);
|
|
|
+ }
|
|
|
+ else if (USART_GetITStatus(uartx, USART_IT_IDLE) == SET)
|
|
|
+ {
|
|
|
+ if (rx_dma)
|
|
|
+ {
|
|
|
+ DMA_Cmd(rx_dma, DISABLE);
|
|
|
+ uint32_t dma_cnt = rx_dma_buff_size -
|
|
|
+ DMA_GetCurrDataCounter(rx_dma);
|
|
|
+ if (dma_cnt)
|
|
|
+ {
|
|
|
+ rkfifo_in(rx_fifo, &rx_dma_buff[0], dma_cnt);
|
|
|
+ }
|
|
|
+ //重新设置传输数据长度
|
|
|
+ DMA_SetCurrDataCounter(rx_dma, uart->_config->_dma_rx_buff_size);
|
|
|
+ //打开DMA
|
|
|
+ DMA_Cmd(rx_dma, ENABLE);
|
|
|
+ }
|
|
|
+
|
|
|
+ uartx->SR;
|
|
|
+ uartx->DR;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ uartx->SR;
|
|
|
+ uartx->DR;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void _uart_tx_dma_isr_callback(struct stm32_uart *uart)
|
|
|
+{
|
|
|
+ DMA_Stream_TypeDef *tx_dma = uart->_config->_tx_dma;
|
|
|
+ rkfifo_t *tx_fifo = &uart->_config->_tx_fifo;
|
|
|
+ uint32_t tcif = uart->_config->_tx_dma_tcif;
|
|
|
+ uint32_t teif = uart->_config->_tx_dma_teif;
|
|
|
+
|
|
|
+ if (DMA_GetITStatus(tx_dma, tcif) == SET)
|
|
|
+ {
|
|
|
+ DMA_ClearITPendingBit(tx_dma, tcif);
|
|
|
+ DMA_Cmd(tx_dma, DISABLE);
|
|
|
+
|
|
|
+ // fifo 中是否还有数据, 如果还有数据, 则读取到 dma buff 中并进行发送
|
|
|
+ uint8_t *dma_buff = uart->_config->_dma_tx_buff;
|
|
|
+ uint32_t dma_buff_size = uart->_config->_dma_tx_buff_size;
|
|
|
+ uint32_t count = rkfifo_out(tx_fifo, dma_buff, dma_buff_size);
|
|
|
+ if (count > 0)
|
|
|
+ {
|
|
|
+ DMA_SetCurrDataCounter(tx_dma, count);
|
|
|
+ DMA_Cmd(tx_dma, ENABLE);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ // 数据发送完成,在多线程时可以抛出信号量
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else if (DMA_GetITStatus(tx_dma, teif) == SET)
|
|
|
+ {
|
|
|
+ DMA_ClearITPendingBit(tx_dma, teif);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void _uart_rx_dma_isr_callback(struct stm32_uart *uart)
|
|
|
+{
|
|
|
+ DMA_Stream_TypeDef *rx_dma = uart->_config->_rx_dma;
|
|
|
+ rkfifo_t *rx_fifo = &uart->_config->_rx_fifo;
|
|
|
+ uint32_t tcif = uart->_config->_rx_dma_tcif;
|
|
|
+ uint32_t teif = uart->_config->_rx_dma_teif;
|
|
|
+
|
|
|
+ if (DMA_GetITStatus(rx_dma, tcif) == SET)
|
|
|
+ {
|
|
|
+ DMA_ClearITPendingBit(rx_dma, tcif);
|
|
|
+ DMA_Cmd(rx_dma, DISABLE);
|
|
|
+
|
|
|
+ uint8_t *dma_buff = uart->_config->_dma_rx_buff;
|
|
|
+ uint32_t dma_buff_size = uart->_config->_dma_rx_buff_size;
|
|
|
+
|
|
|
+ uint32_t dma_cnt = dma_buff_size - DMA_GetCurrDataCounter(rx_dma);
|
|
|
+ if (dma_cnt)
|
|
|
+ {
|
|
|
+ rkfifo_in(rx_fifo, &dma_buff[0], dma_cnt);
|
|
|
+ }
|
|
|
+ //重新设置传输数据长度
|
|
|
+ DMA_SetCurrDataCounter(rx_dma, dma_buff_size);
|
|
|
+ //打开DMA
|
|
|
+ DMA_Cmd(rx_dma, ENABLE);
|
|
|
+ }
|
|
|
+ else if (DMA_GetITStatus(rx_dma, teif) == SET)
|
|
|
+ {
|
|
|
+ DMA_ClearITPendingBit(rx_dma, teif);
|
|
|
+ }
|
|
|
+}
|
|
|
+/**--------------------------- UART1 -----------------------------------------*/
|
|
|
+#ifdef DRV_USING_UART1
|
|
|
+static uint8_t u1_rx_fifo_buff[UART1_RX_FIFO_BUFFER_LEN] = {0};
|
|
|
+static uint8_t u1_tx_fifo_buff[UART1_TX_FIFO_BUFFER_LEN] = {0};
|
|
|
+#ifdef UART1_TX_USING_DMA
|
|
|
+static uint8_t usart1_dma_tx_buf[UART1_TX_DMA_BUFFER_LEN] = {0};
|
|
|
+#endif
|
|
|
+#ifdef UART1_RX_USING_DMA
|
|
|
+static uint8_t usart1_dma_rx_buf[UART1_RX_DMA_BUFFER_LEN] = {0};
|
|
|
+#endif
|
|
|
+
|
|
|
+struct stm32_uart_config _u1_config = {
|
|
|
+ .uartx = USART1,
|
|
|
+ ._tx_port = GPIOA,
|
|
|
+ ._tx_pin = GPIO_Pin_9,
|
|
|
+ ._rx_port = GPIOA,
|
|
|
+ ._rx_pin = GPIO_Pin_10,
|
|
|
+ ._uart_irq_channel = USART1_IRQn,
|
|
|
+
|
|
|
+ ._tx_fifo_buff = u1_tx_fifo_buff,
|
|
|
+ ._tx_fifo_buff_size = sizeof(u1_tx_fifo_buff),
|
|
|
+ ._rx_fifo_buff = u1_rx_fifo_buff,
|
|
|
+ ._rx_fifo_buff_size = sizeof(u1_rx_fifo_buff),
|
|
|
+
|
|
|
+#ifdef UART1_RX_USING_DMA
|
|
|
+ ._rx_dma = DMA2_Stream2,
|
|
|
+ ._rx_dma_tcif = DMA_IT_TCIF2,
|
|
|
+ ._rx_dma_teif = DMA_IT_TEIF2,
|
|
|
+ ._rx_dma_channel = DMA_Channel_4,
|
|
|
+ ._dma_rx_buff = usart1_dma_rx_buf,
|
|
|
+ ._dma_rx_buff_size = sizeof(usart1_dma_rx_buf),
|
|
|
+ ._rx_dma_irq_channel = DMA2_Stream2_IRQn,
|
|
|
+#else
|
|
|
+ ._rx_dma = NULL,
|
|
|
+#endif // USART1_RX_USING_DMA
|
|
|
+
|
|
|
+#ifdef UART1_TX_USING_DMA
|
|
|
+ ._tx_dma = DMA2_Stream7,
|
|
|
+ ._tx_dma_tcif = DMA_IT_TCIF7,
|
|
|
+ ._tx_dma_teif = DMA_IT_TEIF7,
|
|
|
+ ._tx_dma_channel = DMA_Channel_4,
|
|
|
+ ._dma_tx_buff = usart1_dma_tx_buf,
|
|
|
+ ._dma_tx_buff_size = sizeof(usart1_dma_tx_buf),
|
|
|
+ ._tx_dma_irq_channel = DMA2_Stream7_IRQn,
|
|
|
+#else
|
|
|
+ ._tx_dma = NULL,
|
|
|
+#endif // USART1_TX_USING_DMA
|
|
|
+};
|
|
|
+
|
|
|
+static uint32_t u1_write_data(const void *pdata, uint32_t len)
|
|
|
+{
|
|
|
+ return uart_tx_data(&_u1_config, pdata, len);
|
|
|
+}
|
|
|
+static uint32_t u1_read_data(void *pdata, uint32_t len)
|
|
|
+{
|
|
|
+ return uart_rx_data(&_u1_config, pdata, len);
|
|
|
+}
|
|
|
+static int u1_init(uint32_t bps)
|
|
|
+{
|
|
|
+ return uart_init(&_u1_config, bps);
|
|
|
+}
|
|
|
+
|
|
|
+static struct stm32_uart_ops _u1_ops = {
|
|
|
+ .init = u1_init,
|
|
|
+ .read = u1_read_data,
|
|
|
+ .write = u1_write_data};
|
|
|
+
|
|
|
+static struct stm32_uart uart1 = {
|
|
|
+ ._config = &_u1_config,
|
|
|
+ .ops = &_u1_ops};
|
|
|
+
|
|
|
+void USART1_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_isr_callback(&uart1);
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef UART1_TX_USING_DMA
|
|
|
+void DMA2_Stream7_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_tx_dma_isr_callback(&uart1);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef UART1_RX_USING_DMA
|
|
|
+void DMA2_Stream2_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_rx_dma_isr_callback(&uart1);
|
|
|
+}
|
|
|
+#endif
|
|
|
+#endif // DRV_USING_UART1
|
|
|
+
|
|
|
+/**--------------------------- UART2 -----------------------------------------*/
|
|
|
+#ifdef DRV_USING_UART2
|
|
|
+static uint8_t u2_rx_fifo_buff[UART2_RX_FIFO_BUFFER_LEN] = {0};
|
|
|
+static uint8_t u2_tx_fifo_buff[UART2_TX_FIFO_BUFFER_LEN] = {0};
|
|
|
+#ifdef UART2_TX_USING_DMA
|
|
|
+static uint8_t usart2_dma_tx_buf[UART2_TX_DMA_BUFFER_LEN] = {0};
|
|
|
+#endif
|
|
|
+#ifdef UART2_RX_USING_DMA
|
|
|
+static uint8_t usart2_dma_rx_buf[UART2_RX_DMA_BUFFER_LEN] = {0};
|
|
|
+#endif
|
|
|
+
|
|
|
+struct stm32_uart_config _u2_config = {
|
|
|
+ .uartx = USART2,
|
|
|
+ ._tx_port = GPIOA,
|
|
|
+ ._tx_pin = GPIO_Pin_2,
|
|
|
+ ._rx_port = GPIOA,
|
|
|
+ ._rx_pin = GPIO_Pin_3,
|
|
|
+ ._uart_irq_channel = USART2_IRQn,
|
|
|
+
|
|
|
+ ._tx_fifo_buff = u2_tx_fifo_buff,
|
|
|
+ ._tx_fifo_buff_size = sizeof(u2_tx_fifo_buff),
|
|
|
+ ._rx_fifo_buff = u2_rx_fifo_buff,
|
|
|
+ ._rx_fifo_buff_size = sizeof(u2_rx_fifo_buff),
|
|
|
+
|
|
|
+#ifdef UART2_RX_USING_DMA
|
|
|
+ ._rx_dma = DMA1_Stream5,
|
|
|
+ ._rx_dma_tcif = DMA_IT_TCIF5,
|
|
|
+ ._rx_dma_teif = DMA_IT_TEIF5,
|
|
|
+ ._rx_dma_channel = DMA_Channel_4,
|
|
|
+ ._dma_rx_buff = usart2_dma_rx_buf,
|
|
|
+ ._dma_rx_buff_size = sizeof(usart2_dma_rx_buf),
|
|
|
+ ._rx_dma_irq_channel = DMA1_Stream5_IRQn,
|
|
|
+#else
|
|
|
+ ._rx_dma = NULL,
|
|
|
+#endif // USART1_RX_USING_DMA
|
|
|
+
|
|
|
+#ifdef UART2_TX_USING_DMA
|
|
|
+ ._tx_dma = DMA1_Stream6,
|
|
|
+ ._tx_dma_tcif = DMA_IT_TCIF6,
|
|
|
+ ._tx_dma_teif = DMA_IT_TEIF6,
|
|
|
+ ._tx_dma_channel = DMA_Channel_4,
|
|
|
+ ._dma_tx_buff = usart2_dma_tx_buf,
|
|
|
+ ._dma_tx_buff_size = sizeof(usart2_dma_tx_buf),
|
|
|
+ ._tx_dma_irq_channel = DMA1_Stream6_IRQn,
|
|
|
+#else
|
|
|
+ ._tx_dma = NULL,
|
|
|
+#endif // USART2_TX_USING_DMA
|
|
|
+};
|
|
|
+
|
|
|
+static uint32_t u2_write_data(const void *pdata, uint32_t len)
|
|
|
+{
|
|
|
+ return uart_tx_data(&_u2_config, pdata, len);
|
|
|
+}
|
|
|
+static uint32_t u2_read_data(void *pdata, uint32_t len)
|
|
|
+{
|
|
|
+ return uart_rx_data(&_u2_config, pdata, len);
|
|
|
+}
|
|
|
+static int u2_init(uint32_t bps)
|
|
|
+{
|
|
|
+ return uart_init(&_u2_config, bps);
|
|
|
+}
|
|
|
+
|
|
|
+static struct stm32_uart_ops _u2_ops = {
|
|
|
+ .init = u2_init,
|
|
|
+ .read = u2_read_data,
|
|
|
+ .write = u2_write_data};
|
|
|
+
|
|
|
+static struct stm32_uart uart2 = {
|
|
|
+ ._config = &_u2_config,
|
|
|
+ .ops = &_u2_ops};
|
|
|
+
|
|
|
+void USART2_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_isr_callback(&uart2);
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef UART2_TX_USING_DMA
|
|
|
+void DMA1_Stream6_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_tx_dma_isr_callback(&uart1);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef UART2_RX_USING_DMA
|
|
|
+void DMA1_Stream5_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_rx_dma_isr_callback(&uart1);
|
|
|
+}
|
|
|
+#endif
|
|
|
+#endif // DRV_USING_UART2
|
|
|
+
|
|
|
+/**--------------------------- UART3 -----------------------------------------*/
|
|
|
+
|
|
|
+
|
|
|
+/**--------------------------- UART4 -----------------------------------------*/
|
|
|
+#ifdef DRV_USING_UART4
|
|
|
+static uint8_t u4_rx_fifo_buff[UART4_RX_FIFO_BUFFER_LEN] = {0};
|
|
|
+static uint8_t u4_tx_fifo_buff[UART4_TX_FIFO_BUFFER_LEN] = {0};
|
|
|
+#ifdef UART4_TX_USING_DMA
|
|
|
+static uint8_t u4_dma_tx_buf[UART4_TX_DMA_BUFFER_LEN] = {0};
|
|
|
+#endif
|
|
|
+#ifdef UART4_RX_USING_DMA
|
|
|
+static uint8_t u4_dma_rx_buf[UART4_RX_DMA_BUFFER_LEN] = {0};
|
|
|
+#endif
|
|
|
+
|
|
|
+struct stm32_uart_config _u4_config = {
|
|
|
+ .uartx = UART4,
|
|
|
+ ._tx_port = GPIOA,
|
|
|
+ ._tx_pin = GPIO_Pin_0,
|
|
|
+ ._rx_port = GPIOA,
|
|
|
+ ._rx_pin = GPIO_Pin_1,
|
|
|
+ ._uart_irq_channel = UART4_IRQn,
|
|
|
+
|
|
|
+ ._tx_fifo_buff = u4_tx_fifo_buff,
|
|
|
+ ._tx_fifo_buff_size = sizeof(u4_tx_fifo_buff),
|
|
|
+ ._rx_fifo_buff = u4_rx_fifo_buff,
|
|
|
+ ._rx_fifo_buff_size = sizeof(u4_rx_fifo_buff),
|
|
|
+
|
|
|
+#ifdef UART4_RX_USING_DMA
|
|
|
+ ._rx_dma = DMA1_Stream2,
|
|
|
+ ._rx_dma_tcif = DMA_IT_TCIF2,
|
|
|
+ ._rx_dma_teif = DMA_IT_TEIF2,
|
|
|
+ ._rx_dma_channel = DMA_Channel_4,
|
|
|
+ ._dma_rx_buff = u4_dma_rx_buf,
|
|
|
+ ._dma_rx_buff_size = sizeof(u4_dma_rx_buf),
|
|
|
+ ._rx_dma_irq_channel = DMA1_Stream2_IRQn,
|
|
|
+#else
|
|
|
+ ._rx_dma = NULL,
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef UART4_TX_USING_DMA
|
|
|
+ ._tx_dma = DMA1_Stream4,
|
|
|
+ ._tx_dma_tcif = DMA_IT_TCIF4,
|
|
|
+ ._tx_dma_teif = DMA_IT_TEIF4,
|
|
|
+ ._tx_dma_channel = DMA_Channel_4,
|
|
|
+ ._dma_tx_buff = u4_dma_tx_buf,
|
|
|
+ ._dma_tx_buff_size = sizeof(u4_dma_tx_buf),
|
|
|
+ ._tx_dma_irq_channel = DMA1_Stream4_IRQn,
|
|
|
+#else
|
|
|
+ ._tx_dma = NULL,
|
|
|
+#endif
|
|
|
+};
|
|
|
+
|
|
|
+static uint32_t u4_write_data(const void *pdata, uint32_t len)
|
|
|
+{
|
|
|
+ return uart_tx_data(&_u4_config, pdata, len);
|
|
|
+}
|
|
|
+static uint32_t u4_read_data(void *pdata, uint32_t len)
|
|
|
+{
|
|
|
+ return uart_rx_data(&_u4_config, pdata, len);
|
|
|
+}
|
|
|
+static int u4_init(uint32_t bps)
|
|
|
+{
|
|
|
+ return uart_init(&_u4_config, bps);
|
|
|
+}
|
|
|
+
|
|
|
+static struct stm32_uart_ops _u4_ops = {
|
|
|
+ .init = u4_init,
|
|
|
+ .read = u4_read_data,
|
|
|
+ .write = u4_write_data};
|
|
|
+
|
|
|
+static struct stm32_uart uart4 = {
|
|
|
+ ._config = &_u4_config,
|
|
|
+ .ops = &_u4_ops};
|
|
|
+
|
|
|
+void UART4_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_isr_callback(&uart4);
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef UART4_RX_USING_DMA
|
|
|
+void DMA1_Stream2_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_rx_dma_isr_callback(&uart4);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef UART4_TX_USING_DMA
|
|
|
+void DMA1_Stream4_IRQHandler(void)
|
|
|
+{
|
|
|
+ _uart_tx_dma_isr_callback(&uart4);
|
|
|
+}
|
|
|
+#endif
|
|
|
+#endif // DRV_USING_UART4
|
|
|
+
|
|
|
+struct stm32_uart *uart_find(const char *name)
|
|
|
+{
|
|
|
+ struct stm32_uart *uart = NULL;
|
|
|
+ if (strncmp(name, "uart1", 5) == 0)
|
|
|
+ {
|
|
|
+#ifdef DRV_USING_UART1
|
|
|
+ uart = &uart1;
|
|
|
+#endif // DEBUG
|
|
|
+ }
|
|
|
+ else if (strncmp(name, "uart2", 5) == 0)
|
|
|
+ {
|
|
|
+#ifdef DRV_USING_UART2
|
|
|
+ uart = &uart2;
|
|
|
+#endif // DEBUG
|
|
|
+ }
|
|
|
+ else if (strncmp(name, "uart3", 5) == 0)
|
|
|
+ {
|
|
|
+#ifdef DRV_USING_UART3
|
|
|
+ uart = &uart3;
|
|
|
+#endif // DEBUG
|
|
|
+ }
|
|
|
+ else if (strncmp(name, "uart4", 5) == 0)
|
|
|
+ {
|
|
|
+#ifdef DRV_USING_UART4
|
|
|
+ uart = &uart4;
|
|
|
+#endif // DEBUG
|
|
|
+ }
|
|
|
+ else if (strncmp(name, "uart5", 5) == 0)
|
|
|
+ {
|
|
|
+#ifdef DRV_USING_UART5
|
|
|
+ uart = &uart5;
|
|
|
+#endif // DEBUG
|
|
|
+ }
|
|
|
+ else if (strncmp(name, "uart6", 5) == 0)
|
|
|
+ {
|
|
|
+#ifdef DRV_USING_UART6
|
|
|
+ uart = &uart6;
|
|
|
+#endif // DEBUG
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ uart = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ return uart;
|
|
|
+}
|