FOC_TEST/user/note.txt

1 After spending considerable time troubleshooting incorrect PWM output frequency(set 10kHz but look at 3.2kHz why???), 
the root cause was finally identified: the system clock was misconfigured due to an HSE_VALUE mismatch.
Actual SYSCLK = 168MHz × (8MHz / 25MHz) = 53.76MHz    3.2*25/8 = 10  amazing!!!
2 Incorrect DMA Channel Configuration : ADC3 was configured to use DMA2_Stream0 and Channel0,
but according to STM32F4xx reference manual, ADC3 requires DMA2_Stream1 and Channel2.
3 Configuration Order Problem : ADC3 was initialized before ADC1. When ADC1 configuration called ADC_DeInit(), 
it reset all ADC peripherals including ADC3, clearing its configuration.