V9_PMU302_Bootloader/build/system_stm32f3xx.lst

ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 1


   1              		.cpu cortex-m4
   2              		.arch armv7e-m
   3              		.fpu fpv4-sp-d16
   4              		.eabi_attribute 27, 1
   5              		.eabi_attribute 28, 1
   6              		.eabi_attribute 20, 1
   7              		.eabi_attribute 21, 1
   8              		.eabi_attribute 23, 3
   9              		.eabi_attribute 24, 1
  10              		.eabi_attribute 25, 1
  11              		.eabi_attribute 26, 1
  12              		.eabi_attribute 30, 2
  13              		.eabi_attribute 34, 1
  14              		.eabi_attribute 18, 4
  15              		.file	"system_stm32f3xx.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.section	.text.SystemInit,"ax",%progbits
  20              		.align	1
  21              		.p2align 2,,3
  22              		.global	SystemInit
  23              		.syntax unified
  24              		.thumb
  25              		.thumb_func
  27              	SystemInit:
  28              	.LFB130:
  29              		.file 1 "Core/Src/system_stm32f3xx.c"
   1:Core/Src/system_stm32f3xx.c **** /**
   2:Core/Src/system_stm32f3xx.c ****   ******************************************************************************
   3:Core/Src/system_stm32f3xx.c ****   * @file    system_stm32f3xx.c
   4:Core/Src/system_stm32f3xx.c ****   * @author  MCD Application Team
   5:Core/Src/system_stm32f3xx.c ****   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   6:Core/Src/system_stm32f3xx.c ****   *
   7:Core/Src/system_stm32f3xx.c ****   * 1. This file provides two functions and one global variable to be called from
   8:Core/Src/system_stm32f3xx.c ****   *    user application:
   9:Core/Src/system_stm32f3xx.c ****   *      - SystemInit(): This function is called at startup just after reset and 
  10:Core/Src/system_stm32f3xx.c ****   *                      before branch to main program. This call is made inside
  11:Core/Src/system_stm32f3xx.c ****   *                      the "startup_stm32f3xx.s" file.
  12:Core/Src/system_stm32f3xx.c ****   *
  13:Core/Src/system_stm32f3xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  14:Core/Src/system_stm32f3xx.c ****   *                                  by the user application to setup the SysTick
  15:Core/Src/system_stm32f3xx.c ****   *                                  timer or configure other parameters.
  16:Core/Src/system_stm32f3xx.c ****   *
  17:Core/Src/system_stm32f3xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18:Core/Src/system_stm32f3xx.c ****   *                                 be called whenever the core clock is changed
  19:Core/Src/system_stm32f3xx.c ****   *                                 during program execution.
  20:Core/Src/system_stm32f3xx.c ****   *
  21:Core/Src/system_stm32f3xx.c ****   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  22:Core/Src/system_stm32f3xx.c ****   *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
  23:Core/Src/system_stm32f3xx.c ****   *    configure the system clock before to branch to main program.
  24:Core/Src/system_stm32f3xx.c ****   *
  25:Core/Src/system_stm32f3xx.c ****   * 3. This file configures the system clock as follows:
  26:Core/Src/system_stm32f3xx.c ****   *=============================================================================
  27:Core/Src/system_stm32f3xx.c ****   *                         Supported STM32F3xx device
  28:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  29:Core/Src/system_stm32f3xx.c ****   *        System Clock source                    | HSI
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 2


  30:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  31:Core/Src/system_stm32f3xx.c ****   *        SYSCLK(Hz)                             | 8000000
  32:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  33:Core/Src/system_stm32f3xx.c ****   *        HCLK(Hz)                               | 8000000
  34:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  35:Core/Src/system_stm32f3xx.c ****   *        AHB Prescaler                          | 1
  36:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  37:Core/Src/system_stm32f3xx.c ****   *        APB2 Prescaler                         | 1
  38:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  39:Core/Src/system_stm32f3xx.c ****   *        APB1 Prescaler                         | 1
  40:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  41:Core/Src/system_stm32f3xx.c ****   *        USB Clock                              | DISABLE
  42:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  43:Core/Src/system_stm32f3xx.c ****   *=============================================================================
  44:Core/Src/system_stm32f3xx.c ****   ******************************************************************************
  45:Core/Src/system_stm32f3xx.c ****   * @attention
  46:Core/Src/system_stm32f3xx.c ****   *
  47:Core/Src/system_stm32f3xx.c ****   * Copyright (c) 2016 STMicroelectronics.
  48:Core/Src/system_stm32f3xx.c ****   * All rights reserved.
  49:Core/Src/system_stm32f3xx.c ****   *
  50:Core/Src/system_stm32f3xx.c ****   * This software is licensed under terms that can be found in the LICENSE file
  51:Core/Src/system_stm32f3xx.c ****   * in the root directory of this software component.
  52:Core/Src/system_stm32f3xx.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  53:Core/Src/system_stm32f3xx.c ****   *
  54:Core/Src/system_stm32f3xx.c ****   ******************************************************************************
  55:Core/Src/system_stm32f3xx.c ****   */
  56:Core/Src/system_stm32f3xx.c **** 
  57:Core/Src/system_stm32f3xx.c **** /** @addtogroup CMSIS
  58:Core/Src/system_stm32f3xx.c ****   * @{
  59:Core/Src/system_stm32f3xx.c ****   */
  60:Core/Src/system_stm32f3xx.c **** 
  61:Core/Src/system_stm32f3xx.c **** /** @addtogroup stm32f3xx_system
  62:Core/Src/system_stm32f3xx.c ****   * @{
  63:Core/Src/system_stm32f3xx.c ****   */
  64:Core/Src/system_stm32f3xx.c **** 
  65:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Includes
  66:Core/Src/system_stm32f3xx.c ****   * @{
  67:Core/Src/system_stm32f3xx.c ****   */
  68:Core/Src/system_stm32f3xx.c **** 
  69:Core/Src/system_stm32f3xx.c **** #include "stm32f3xx.h"
  70:Core/Src/system_stm32f3xx.c **** 
  71:Core/Src/system_stm32f3xx.c **** /**
  72:Core/Src/system_stm32f3xx.c ****   * @}
  73:Core/Src/system_stm32f3xx.c ****   */
  74:Core/Src/system_stm32f3xx.c **** 
  75:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
  76:Core/Src/system_stm32f3xx.c ****   * @{
  77:Core/Src/system_stm32f3xx.c ****   */
  78:Core/Src/system_stm32f3xx.c **** 
  79:Core/Src/system_stm32f3xx.c **** /**
  80:Core/Src/system_stm32f3xx.c ****   * @}
  81:Core/Src/system_stm32f3xx.c ****   */
  82:Core/Src/system_stm32f3xx.c **** 
  83:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Defines
  84:Core/Src/system_stm32f3xx.c ****   * @{
  85:Core/Src/system_stm32f3xx.c ****   */
  86:Core/Src/system_stm32f3xx.c **** #if !defined  (HSE_VALUE) 
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 3


  87:Core/Src/system_stm32f3xx.c ****   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
  88:Core/Src/system_stm32f3xx.c ****                                                 This value can be provided and adapted by the user 
  89:Core/Src/system_stm32f3xx.c **** #endif /* HSE_VALUE */
  90:Core/Src/system_stm32f3xx.c **** 
  91:Core/Src/system_stm32f3xx.c **** #if !defined  (HSI_VALUE)
  92:Core/Src/system_stm32f3xx.c ****   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
  93:Core/Src/system_stm32f3xx.c ****                                                 This value can be provided and adapted by the user 
  94:Core/Src/system_stm32f3xx.c **** #endif /* HSI_VALUE */
  95:Core/Src/system_stm32f3xx.c **** 
  96:Core/Src/system_stm32f3xx.c **** /* Note: Following vector table addresses must be defined in line with linker
  97:Core/Src/system_stm32f3xx.c ****          configuration. */
  98:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
  99:Core/Src/system_stm32f3xx.c ****      anywhere in Flash or Sram, else the vector table is kept at the automatic
 100:Core/Src/system_stm32f3xx.c ****      remap of boot address selected */
 101:Core/Src/system_stm32f3xx.c **** /* #define USER_VECT_TAB_ADDRESS */
 102:Core/Src/system_stm32f3xx.c **** 
 103:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 104:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
 105:Core/Src/system_stm32f3xx.c ****      in Sram else user remap will be done in Flash. */
 106:Core/Src/system_stm32f3xx.c **** /* #define VECT_TAB_SRAM */
 107:Core/Src/system_stm32f3xx.c **** #if defined(VECT_TAB_SRAM)
 108:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
 109:Core/Src/system_stm32f3xx.c ****                                                      This value must be a multiple of 0x200. */
 110:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
 111:Core/Src/system_stm32f3xx.c ****                                                      This value must be a multiple of 0x200. */
 112:Core/Src/system_stm32f3xx.c **** #else
 113:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
 114:Core/Src/system_stm32f3xx.c ****                                                      This value must be a multiple of 0x200. */
 115:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
 116:Core/Src/system_stm32f3xx.c ****                                                      This value must be a multiple of 0x200. */
 117:Core/Src/system_stm32f3xx.c **** #endif /* VECT_TAB_SRAM */
 118:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 119:Core/Src/system_stm32f3xx.c **** 
 120:Core/Src/system_stm32f3xx.c **** /******************************************************************************/
 121:Core/Src/system_stm32f3xx.c **** /**
 122:Core/Src/system_stm32f3xx.c ****   * @}
 123:Core/Src/system_stm32f3xx.c ****   */
 124:Core/Src/system_stm32f3xx.c **** 
 125:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Macros
 126:Core/Src/system_stm32f3xx.c ****   * @{
 127:Core/Src/system_stm32f3xx.c ****   */
 128:Core/Src/system_stm32f3xx.c **** 
 129:Core/Src/system_stm32f3xx.c **** /**
 130:Core/Src/system_stm32f3xx.c ****   * @}
 131:Core/Src/system_stm32f3xx.c ****   */
 132:Core/Src/system_stm32f3xx.c **** 
 133:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Variables
 134:Core/Src/system_stm32f3xx.c ****   * @{
 135:Core/Src/system_stm32f3xx.c ****   */
 136:Core/Src/system_stm32f3xx.c ****   /* This variable is updated in three ways:
 137:Core/Src/system_stm32f3xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
 138:Core/Src/system_stm32f3xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 139:Core/Src/system_stm32f3xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 140:Core/Src/system_stm32f3xx.c ****          Note: If you use this function to configure the system clock there is no need to
 141:Core/Src/system_stm32f3xx.c ****                call the 2 first functions listed above, since SystemCoreClock variable is 
 142:Core/Src/system_stm32f3xx.c ****                updated automatically.
 143:Core/Src/system_stm32f3xx.c ****   */
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 4


 144:Core/Src/system_stm32f3xx.c **** uint32_t SystemCoreClock = 8000000;
 145:Core/Src/system_stm32f3xx.c **** 
 146:Core/Src/system_stm32f3xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 147:Core/Src/system_stm32f3xx.c **** const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 148:Core/Src/system_stm32f3xx.c **** 
 149:Core/Src/system_stm32f3xx.c **** /**
 150:Core/Src/system_stm32f3xx.c ****   * @}
 151:Core/Src/system_stm32f3xx.c ****   */
 152:Core/Src/system_stm32f3xx.c **** 
 153:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
 154:Core/Src/system_stm32f3xx.c ****   * @{
 155:Core/Src/system_stm32f3xx.c ****   */
 156:Core/Src/system_stm32f3xx.c **** 
 157:Core/Src/system_stm32f3xx.c **** /**
 158:Core/Src/system_stm32f3xx.c ****   * @}
 159:Core/Src/system_stm32f3xx.c ****   */
 160:Core/Src/system_stm32f3xx.c **** 
 161:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Functions
 162:Core/Src/system_stm32f3xx.c ****   * @{
 163:Core/Src/system_stm32f3xx.c ****   */
 164:Core/Src/system_stm32f3xx.c **** 
 165:Core/Src/system_stm32f3xx.c **** /**
 166:Core/Src/system_stm32f3xx.c ****   * @brief  Setup the microcontroller system
 167:Core/Src/system_stm32f3xx.c ****   * @param  None
 168:Core/Src/system_stm32f3xx.c ****   * @retval None
 169:Core/Src/system_stm32f3xx.c ****   */
 170:Core/Src/system_stm32f3xx.c **** void SystemInit(void)
 171:Core/Src/system_stm32f3xx.c **** {
  30              		.loc 1 171 1 view -0
  31              		.cfi_startproc
  32              		@ args = 0, pretend = 0, frame = 0
  33              		@ frame_needed = 0, uses_anonymous_args = 0
  34              		@ link register save eliminated.
 172:Core/Src/system_stm32f3xx.c **** /* FPU settings --------------------------------------------------------------*/
 173:Core/Src/system_stm32f3xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 174:Core/Src/system_stm32f3xx.c ****   SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
  35              		.loc 1 174 3 view .LVU1
  36              		.loc 1 174 14 is_stmt 0 view .LVU2
  37 0000 034A     		ldr	r2, .L3
  38 0002 D2F88830 		ldr	r3, [r2, #136]
  39 0006 43F47003 		orr	r3, r3, #15728640
  40 000a C2F88830 		str	r3, [r2, #136]
 175:Core/Src/system_stm32f3xx.c **** #endif
 176:Core/Src/system_stm32f3xx.c **** 
 177:Core/Src/system_stm32f3xx.c ****   /* Configure the Vector Table location -------------------------------------*/
 178:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 179:Core/Src/system_stm32f3xx.c ****   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM 
 180:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 181:Core/Src/system_stm32f3xx.c **** }
  41              		.loc 1 181 1 view .LVU3
  42 000e 7047     		bx	lr
  43              	.L4:
  44              		.align	2
  45              	.L3:
  46 0010 00ED00E0 		.word	-536810240
  47              		.cfi_endproc
  48              	.LFE130:
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 5


  50              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
  51              		.align	1
  52              		.p2align 2,,3
  53              		.global	SystemCoreClockUpdate
  54              		.syntax unified
  55              		.thumb
  56              		.thumb_func
  58              	SystemCoreClockUpdate:
  59              	.LFB131:
 182:Core/Src/system_stm32f3xx.c **** 
 183:Core/Src/system_stm32f3xx.c **** /**
 184:Core/Src/system_stm32f3xx.c ****    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 185:Core/Src/system_stm32f3xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 186:Core/Src/system_stm32f3xx.c ****   *         be used by the user application to setup the SysTick timer or configure
 187:Core/Src/system_stm32f3xx.c ****   *         other parameters.
 188:Core/Src/system_stm32f3xx.c ****   *
 189:Core/Src/system_stm32f3xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
 190:Core/Src/system_stm32f3xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 191:Core/Src/system_stm32f3xx.c ****   *         based on this variable will be incorrect.
 192:Core/Src/system_stm32f3xx.c ****   *
 193:Core/Src/system_stm32f3xx.c ****   * @note   - The system frequency computed by this function is not the real
 194:Core/Src/system_stm32f3xx.c ****   *           frequency in the chip. It is calculated based on the predefined
 195:Core/Src/system_stm32f3xx.c ****   *           constant and the selected clock source:
 196:Core/Src/system_stm32f3xx.c ****   *
 197:Core/Src/system_stm32f3xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 198:Core/Src/system_stm32f3xx.c ****   *
 199:Core/Src/system_stm32f3xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 200:Core/Src/system_stm32f3xx.c ****   *
 201:Core/Src/system_stm32f3xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 202:Core/Src/system_stm32f3xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 203:Core/Src/system_stm32f3xx.c ****   *
 204:Core/Src/system_stm32f3xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
 205:Core/Src/system_stm32f3xx.c ****   *             8 MHz) but the real value may vary depending on the variations
 206:Core/Src/system_stm32f3xx.c ****   *             in voltage and temperature.
 207:Core/Src/system_stm32f3xx.c ****   *
 208:Core/Src/system_stm32f3xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
 209:Core/Src/system_stm32f3xx.c ****   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 210:Core/Src/system_stm32f3xx.c ****   *              frequency of the crystal used. Otherwise, this function may
 211:Core/Src/system_stm32f3xx.c ****   *              have wrong result.
 212:Core/Src/system_stm32f3xx.c ****   *
 213:Core/Src/system_stm32f3xx.c ****   *         - The result of this function could be not correct when using fractional
 214:Core/Src/system_stm32f3xx.c ****   *           value for HSE crystal.
 215:Core/Src/system_stm32f3xx.c ****   *
 216:Core/Src/system_stm32f3xx.c ****   * @param  None
 217:Core/Src/system_stm32f3xx.c ****   * @retval None
 218:Core/Src/system_stm32f3xx.c ****   */
 219:Core/Src/system_stm32f3xx.c **** void SystemCoreClockUpdate (void)
 220:Core/Src/system_stm32f3xx.c **** {
  60              		.loc 1 220 1 is_stmt 1 view -0
  61              		.cfi_startproc
  62              		@ args = 0, pretend = 0, frame = 0
  63              		@ frame_needed = 0, uses_anonymous_args = 0
  64              		@ link register save eliminated.
 221:Core/Src/system_stm32f3xx.c ****   uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
  65              		.loc 1 221 3 view .LVU5
  66              	.LVL0:
 222:Core/Src/system_stm32f3xx.c **** 
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 6


 223:Core/Src/system_stm32f3xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 224:Core/Src/system_stm32f3xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
  67              		.loc 1 224 3 view .LVU6
  68              		.loc 1 224 12 is_stmt 0 view .LVU7
  69 0000 134A     		ldr	r2, .L10
  70 0002 5368     		ldr	r3, [r2, #4]
  71              	.LVL1:
 225:Core/Src/system_stm32f3xx.c **** 
 226:Core/Src/system_stm32f3xx.c ****   switch (tmp)
  72              		.loc 1 226 3 is_stmt 1 view .LVU8
 224:Core/Src/system_stm32f3xx.c **** 
  73              		.loc 1 224 7 is_stmt 0 view .LVU9
  74 0004 03F00C03 		and	r3, r3, #12
  75              	.LVL2:
  76              		.loc 1 226 3 view .LVU10
  77 0008 082B     		cmp	r3, #8
  78 000a 0AD0     		beq	.L9
  79 000c 114B     		ldr	r3, .L10+4
  80              	.LVL3:
  81              	.L6:
 227:Core/Src/system_stm32f3xx.c ****   {
 228:Core/Src/system_stm32f3xx.c ****     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
 229:Core/Src/system_stm32f3xx.c ****       SystemCoreClock = HSI_VALUE;
 230:Core/Src/system_stm32f3xx.c ****       break;
 231:Core/Src/system_stm32f3xx.c ****     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
 232:Core/Src/system_stm32f3xx.c ****       SystemCoreClock = HSE_VALUE;
 233:Core/Src/system_stm32f3xx.c ****       break;
 234:Core/Src/system_stm32f3xx.c ****     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
 235:Core/Src/system_stm32f3xx.c ****       /* Get PLL clock source and multiplication factor ----------------------*/
 236:Core/Src/system_stm32f3xx.c ****       pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
 237:Core/Src/system_stm32f3xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 238:Core/Src/system_stm32f3xx.c ****       pllmull = ( pllmull >> 18) + 2;
 239:Core/Src/system_stm32f3xx.c **** 
 240:Core/Src/system_stm32f3xx.c **** #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
 241:Core/Src/system_stm32f3xx.c ****         predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 242:Core/Src/system_stm32f3xx.c ****       if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
 243:Core/Src/system_stm32f3xx.c ****       {
 244:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 245:Core/Src/system_stm32f3xx.c ****         SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
 246:Core/Src/system_stm32f3xx.c ****       }
 247:Core/Src/system_stm32f3xx.c ****       else
 248:Core/Src/system_stm32f3xx.c ****       {
 249:Core/Src/system_stm32f3xx.c ****         /* HSI oscillator clock selected as PREDIV1 clock entry */
 250:Core/Src/system_stm32f3xx.c ****         SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
 251:Core/Src/system_stm32f3xx.c ****       }
 252:Core/Src/system_stm32f3xx.c **** #else      
 253:Core/Src/system_stm32f3xx.c ****       if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
 254:Core/Src/system_stm32f3xx.c ****       {
 255:Core/Src/system_stm32f3xx.c ****         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 256:Core/Src/system_stm32f3xx.c ****         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 257:Core/Src/system_stm32f3xx.c ****       }
 258:Core/Src/system_stm32f3xx.c ****       else
 259:Core/Src/system_stm32f3xx.c ****       {
 260:Core/Src/system_stm32f3xx.c ****         predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 261:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 262:Core/Src/system_stm32f3xx.c ****         SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
 263:Core/Src/system_stm32f3xx.c ****       }
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 7


 264:Core/Src/system_stm32f3xx.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 265:Core/Src/system_stm32f3xx.c ****       break;
 266:Core/Src/system_stm32f3xx.c ****     default: /* HSI used as system clock */
 267:Core/Src/system_stm32f3xx.c ****       SystemCoreClock = HSI_VALUE;
 268:Core/Src/system_stm32f3xx.c ****       break;
 269:Core/Src/system_stm32f3xx.c ****   }
 270:Core/Src/system_stm32f3xx.c ****   /* Compute HCLK clock frequency ----------------*/
 271:Core/Src/system_stm32f3xx.c ****   /* Get HCLK prescaler */
 272:Core/Src/system_stm32f3xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  82              		.loc 1 272 3 is_stmt 1 view .LVU11
  83              		.loc 1 272 28 is_stmt 0 view .LVU12
  84 000e 104A     		ldr	r2, .L10
  85              		.loc 1 272 22 view .LVU13
  86 0010 1148     		ldr	r0, .L10+8
  87              		.loc 1 272 28 view .LVU14
  88 0012 5268     		ldr	r2, [r2, #4]
  89              	.LVL4:
 273:Core/Src/system_stm32f3xx.c ****   /* HCLK clock frequency */
 274:Core/Src/system_stm32f3xx.c ****   SystemCoreClock >>= tmp;
  90              		.loc 1 274 3 is_stmt 1 view .LVU15
  91              		.loc 1 274 19 is_stmt 0 view .LVU16
  92 0014 1149     		ldr	r1, .L10+12
 272:Core/Src/system_stm32f3xx.c ****   /* HCLK clock frequency */
  93              		.loc 1 272 52 view .LVU17
  94 0016 C2F30312 		ubfx	r2, r2, #4, #4
  95              	.LVL5:
 272:Core/Src/system_stm32f3xx.c ****   /* HCLK clock frequency */
  96              		.loc 1 272 7 view .LVU18
  97 001a 825C     		ldrb	r2, [r0, r2]	@ zero_extendqisi2
  98              		.loc 1 274 19 view .LVU19
  99 001c D340     		lsrs	r3, r3, r2
 100 001e 0B60     		str	r3, [r1]
 275:Core/Src/system_stm32f3xx.c **** }
 101              		.loc 1 275 1 view .LVU20
 102 0020 7047     		bx	lr
 103              	.LVL6:
 104              	.L9:
 236:Core/Src/system_stm32f3xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 105              		.loc 1 236 7 is_stmt 1 view .LVU21
 236:Core/Src/system_stm32f3xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 106              		.loc 1 236 20 is_stmt 0 view .LVU22
 107 0022 5368     		ldr	r3, [r2, #4]
 108              	.LVL7:
 237:Core/Src/system_stm32f3xx.c ****       pllmull = ( pllmull >> 18) + 2;
 109              		.loc 1 237 7 is_stmt 1 view .LVU23
 237:Core/Src/system_stm32f3xx.c ****       pllmull = ( pllmull >> 18) + 2;
 110              		.loc 1 237 22 is_stmt 0 view .LVU24
 111 0024 5168     		ldr	r1, [r2, #4]
 112              	.LVL8:
 238:Core/Src/system_stm32f3xx.c **** 
 113              		.loc 1 238 7 is_stmt 1 view .LVU25
 238:Core/Src/system_stm32f3xx.c **** 
 114              		.loc 1 238 27 is_stmt 0 view .LVU26
 115 0026 C3F38343 		ubfx	r3, r3, #18, #4
 116              	.LVL9:
 253:Core/Src/system_stm32f3xx.c ****       {
 117              		.loc 1 253 10 view .LVU27
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 8


 118 002a C903     		lsls	r1, r1, #15
 119              	.LVL10:
 238:Core/Src/system_stm32f3xx.c **** 
 120              		.loc 1 238 15 view .LVU28
 121 002c 03F10203 		add	r3, r3, #2
 122              	.LVL11:
 253:Core/Src/system_stm32f3xx.c ****       {
 123              		.loc 1 253 7 is_stmt 1 view .LVU29
 253:Core/Src/system_stm32f3xx.c ****       {
 124              		.loc 1 253 10 is_stmt 0 view .LVU30
 125 0030 03D4     		bmi	.L7
 256:Core/Src/system_stm32f3xx.c ****       }
 126              		.loc 1 256 9 is_stmt 1 view .LVU31
 256:Core/Src/system_stm32f3xx.c ****       }
 127              		.loc 1 256 44 is_stmt 0 view .LVU32
 128 0032 0B4A     		ldr	r2, .L10+16
 129 0034 02FB03F3 		mul	r3, r2, r3
 130              	.LVL12:
 256:Core/Src/system_stm32f3xx.c ****       }
 131              		.loc 1 256 44 view .LVU33
 132 0038 E9E7     		b	.L6
 133              	.LVL13:
 134              	.L7:
 260:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 135              		.loc 1 260 9 is_stmt 1 view .LVU34
 260:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 136              		.loc 1 260 28 is_stmt 0 view .LVU35
 137 003a D26A     		ldr	r2, [r2, #44]
 138              	.LVL14:
 262:Core/Src/system_stm32f3xx.c ****       }
 139              		.loc 1 262 9 is_stmt 1 view .LVU36
 262:Core/Src/system_stm32f3xx.c ****       }
 140              		.loc 1 262 38 is_stmt 0 view .LVU37
 141 003c 0549     		ldr	r1, .L10+4
 260:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 142              		.loc 1 260 36 view .LVU38
 143 003e 02F00F02 		and	r2, r2, #15
 144              	.LVL15:
 260:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 145              		.loc 1 260 22 view .LVU39
 146 0042 0132     		adds	r2, r2, #1
 147              	.LVL16:
 262:Core/Src/system_stm32f3xx.c ****       }
 148              		.loc 1 262 38 view .LVU40
 149 0044 B1FBF2F2 		udiv	r2, r1, r2
 150              	.LVL17:
 262:Core/Src/system_stm32f3xx.c ****       }
 151              		.loc 1 262 54 view .LVU41
 152 0048 02FB03F3 		mul	r3, r2, r3
 153              	.LVL18:
 262:Core/Src/system_stm32f3xx.c ****       }
 154              		.loc 1 262 54 view .LVU42
 155 004c DFE7     		b	.L6
 156              	.L11:
 157 004e 00BF     		.align	2
 158              	.L10:
 159 0050 00100240 		.word	1073876992
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 9


 160 0054 00127A00 		.word	8000000
 161 0058 00000000 		.word	.LANCHOR1
 162 005c 00000000 		.word	.LANCHOR0
 163 0060 00093D00 		.word	4000000
 164              		.cfi_endproc
 165              	.LFE131:
 167              		.global	APBPrescTable
 168              		.global	AHBPrescTable
 169              		.global	SystemCoreClock
 170              		.section	.data.SystemCoreClock,"aw"
 171              		.align	2
 172              		.set	.LANCHOR0,. + 0
 175              	SystemCoreClock:
 176 0000 00127A00 		.word	8000000
 177              		.section	.rodata.AHBPrescTable,"a"
 178              		.align	2
 179              		.set	.LANCHOR1,. + 0
 182              	AHBPrescTable:
 183 0000 00000000 		.ascii	"\000\000\000\000\000\000\000\000\001\002\003\004\006"
 183      00000000 
 183      01020304 
 183      06
 184 000d 070809   		.ascii	"\007\010\011"
 185              		.section	.rodata.APBPrescTable,"a"
 186              		.align	2
 189              	APBPrescTable:
 190 0000 00000000 		.ascii	"\000\000\000\000\001\002\003\004"
 190      01020304 
 191              		.text
 192              	.Letext0:
 193              		.file 2 "d:\\arm-gcc\\arm-none-eabi\\include\\machine\\_default_types.h"
 194              		.file 3 "d:\\arm-gcc\\arm-none-eabi\\include\\sys\\_stdint.h"
 195              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
 196              		.file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h"
 197              		.file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
ARM GAS  C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s 			page 10


DEFINED SYMBOLS
                            *ABS*:00000000 system_stm32f3xx.c
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:20     .text.SystemInit:00000000 $t
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:27     .text.SystemInit:00000000 SystemInit
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:46     .text.SystemInit:00000010 $d
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:51     .text.SystemCoreClockUpdate:00000000 $t
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:58     .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:159    .text.SystemCoreClockUpdate:00000050 $d
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:189    .rodata.APBPrescTable:00000000 APBPrescTable
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:182    .rodata.AHBPrescTable:00000000 AHBPrescTable
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:175    .data.SystemCoreClock:00000000 SystemCoreClock
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:171    .data.SystemCoreClock:00000000 $d
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:178    .rodata.AHBPrescTable:00000000 $d
C:\Users\zl835\AppData\Local\Temp\cc9aF3u8.s:186    .rodata.APBPrescTable:00000000 $d

NO UNDEFINED SYMBOLS