stm32f3xx_hal_tim_ex.c 85 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f3xx_hal_tim_ex.c
  4. * @author MCD Application Team
  5. * @brief TIM HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Timer Extended peripheral:
  8. * + Time Hall Sensor Interface Initialization
  9. * + Time Hall Sensor Interface Start
  10. * + Time Complementary signal break and dead time configuration
  11. * + Time Master and Slave synchronization configuration
  12. * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
  13. * + Time OCRef clear configuration
  14. * + Timer remapping capabilities configuration
  15. ******************************************************************************
  16. * @attention
  17. *
  18. * Copyright (c) 2016 STMicroelectronics.
  19. * All rights reserved.
  20. *
  21. * This software is licensed under terms that can be found in the LICENSE file
  22. * in the root directory of this software component.
  23. * If no LICENSE file comes with this software, it is provided AS-IS.
  24. *
  25. ******************************************************************************
  26. @verbatim
  27. ==============================================================================
  28. ##### TIMER Extended features #####
  29. ==============================================================================
  30. [..]
  31. The Timer Extended features include:
  32. (#) Complementary outputs with programmable dead-time for :
  33. (++) Output Compare
  34. (++) PWM generation (Edge and Center-aligned Mode)
  35. (++) One-pulse mode output
  36. (#) Synchronization circuit to control the timer with external signals and to
  37. interconnect several timers together.
  38. (#) Break input to put the timer output signals in reset state or in a known state.
  39. (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
  40. positioning purposes
  41. ##### How to use this driver #####
  42. ==============================================================================
  43. [..]
  44. (#) Initialize the TIM low level resources by implementing the following functions
  45. depending on the selected feature:
  46. (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
  47. (#) Initialize the TIM low level resources :
  48. (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
  49. (##) TIM pins configuration
  50. (+++) Enable the clock for the TIM GPIOs using the following function:
  51. __HAL_RCC_GPIOx_CLK_ENABLE();
  52. (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
  53. (#) The external Clock can be configured, if needed (the default clock is the
  54. internal clock from the APBx), using the following function:
  55. HAL_TIM_ConfigClockSource, the clock configuration should be done before
  56. any start function.
  57. (#) Configure the TIM in the desired functioning mode using one of the
  58. initialization function of this driver:
  59. (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
  60. Timer Hall Sensor Interface and the commutation event with the corresponding
  61. Interrupt and DMA request if needed (Note that One Timer is used to interface
  62. with the Hall sensor Interface and another Timer should be used to use
  63. the commutation event).
  64. (#) Activate the TIM peripheral using one of the start functions:
  65. (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
  66. HAL_TIMEx_OCN_Start_IT()
  67. (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
  68. HAL_TIMEx_PWMN_Start_IT()
  69. (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
  70. (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
  71. HAL_TIMEx_HallSensor_Start_IT().
  72. @endverbatim
  73. ******************************************************************************
  74. */
  75. /* Includes ------------------------------------------------------------------*/
  76. #include "stm32f3xx_hal.h"
  77. /** @addtogroup STM32F3xx_HAL_Driver
  78. * @{
  79. */
  80. /** @defgroup TIMEx TIMEx
  81. * @brief TIM Extended HAL module driver
  82. * @{
  83. */
  84. #ifdef HAL_TIM_MODULE_ENABLED
  85. /* Private typedef -----------------------------------------------------------*/
  86. /* Private define ------------------------------------------------------------*/
  87. /* Private macros ------------------------------------------------------------*/
  88. /* Private variables ---------------------------------------------------------*/
  89. /* Private function prototypes -----------------------------------------------*/
  90. static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
  91. static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
  92. static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
  93. /* Exported functions --------------------------------------------------------*/
  94. /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
  95. * @{
  96. */
  97. /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
  98. * @brief Timer Hall Sensor functions
  99. *
  100. @verbatim
  101. ==============================================================================
  102. ##### Timer Hall Sensor functions #####
  103. ==============================================================================
  104. [..]
  105. This section provides functions allowing to:
  106. (+) Initialize and configure TIM HAL Sensor.
  107. (+) De-initialize TIM HAL Sensor.
  108. (+) Start the Hall Sensor Interface.
  109. (+) Stop the Hall Sensor Interface.
  110. (+) Start the Hall Sensor Interface and enable interrupts.
  111. (+) Stop the Hall Sensor Interface and disable interrupts.
  112. (+) Start the Hall Sensor Interface and enable DMA transfers.
  113. (+) Stop the Hall Sensor Interface and disable DMA transfers.
  114. @endverbatim
  115. * @{
  116. */
  117. /**
  118. * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
  119. * @note When the timer instance is initialized in Hall Sensor Interface mode,
  120. * timer channels 1 and channel 2 are reserved and cannot be used for
  121. * other purpose.
  122. * @param htim TIM Hall Sensor Interface handle
  123. * @param sConfig TIM Hall Sensor configuration structure
  124. * @retval HAL status
  125. */
  126. HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
  127. {
  128. TIM_OC_InitTypeDef OC_Config;
  129. /* Check the TIM handle allocation */
  130. if (htim == NULL)
  131. {
  132. return HAL_ERROR;
  133. }
  134. /* Check the parameters */
  135. assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
  136. assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  137. assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  138. assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  139. assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
  140. assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
  141. assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
  142. assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
  143. if (htim->State == HAL_TIM_STATE_RESET)
  144. {
  145. /* Allocate lock resource and initialize it */
  146. htim->Lock = HAL_UNLOCKED;
  147. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  148. /* Reset interrupt callbacks to legacy week callbacks */
  149. TIM_ResetCallback(htim);
  150. if (htim->HallSensor_MspInitCallback == NULL)
  151. {
  152. htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
  153. }
  154. /* Init the low level hardware : GPIO, CLOCK, NVIC */
  155. htim->HallSensor_MspInitCallback(htim);
  156. #else
  157. /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  158. HAL_TIMEx_HallSensor_MspInit(htim);
  159. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  160. }
  161. /* Set the TIM state */
  162. htim->State = HAL_TIM_STATE_BUSY;
  163. /* Configure the Time base in the Encoder Mode */
  164. TIM_Base_SetConfig(htim->Instance, &htim->Init);
  165. /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
  166. TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
  167. /* Reset the IC1PSC Bits */
  168. htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  169. /* Set the IC1PSC value */
  170. htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
  171. /* Enable the Hall sensor interface (XOR function of the three inputs) */
  172. htim->Instance->CR2 |= TIM_CR2_TI1S;
  173. /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
  174. htim->Instance->SMCR &= ~TIM_SMCR_TS;
  175. htim->Instance->SMCR |= TIM_TS_TI1F_ED;
  176. /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
  177. htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  178. htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
  179. /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
  180. OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
  181. OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
  182. OC_Config.OCMode = TIM_OCMODE_PWM2;
  183. OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  184. OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
  185. OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
  186. OC_Config.Pulse = sConfig->Commutation_Delay;
  187. TIM_OC2_SetConfig(htim->Instance, &OC_Config);
  188. /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
  189. register to 101 */
  190. htim->Instance->CR2 &= ~TIM_CR2_MMS;
  191. htim->Instance->CR2 |= TIM_TRGO_OC2REF;
  192. /* Initialize the DMA burst operation state */
  193. htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  194. /* Initialize the TIM channels state */
  195. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  196. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  197. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  198. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  199. /* Initialize the TIM state*/
  200. htim->State = HAL_TIM_STATE_READY;
  201. return HAL_OK;
  202. }
  203. /**
  204. * @brief DeInitializes the TIM Hall Sensor interface
  205. * @param htim TIM Hall Sensor Interface handle
  206. * @retval HAL status
  207. */
  208. HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
  209. {
  210. /* Check the parameters */
  211. assert_param(IS_TIM_INSTANCE(htim->Instance));
  212. htim->State = HAL_TIM_STATE_BUSY;
  213. /* Disable the TIM Peripheral Clock */
  214. __HAL_TIM_DISABLE(htim);
  215. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  216. if (htim->HallSensor_MspDeInitCallback == NULL)
  217. {
  218. htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
  219. }
  220. /* DeInit the low level hardware */
  221. htim->HallSensor_MspDeInitCallback(htim);
  222. #else
  223. /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  224. HAL_TIMEx_HallSensor_MspDeInit(htim);
  225. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  226. /* Change the DMA burst operation state */
  227. htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  228. /* Change the TIM channels state */
  229. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  230. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  231. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  232. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  233. /* Change TIM state */
  234. htim->State = HAL_TIM_STATE_RESET;
  235. /* Release Lock */
  236. __HAL_UNLOCK(htim);
  237. return HAL_OK;
  238. }
  239. /**
  240. * @brief Initializes the TIM Hall Sensor MSP.
  241. * @param htim TIM Hall Sensor Interface handle
  242. * @retval None
  243. */
  244. __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
  245. {
  246. /* Prevent unused argument(s) compilation warning */
  247. UNUSED(htim);
  248. /* NOTE : This function should not be modified, when the callback is needed,
  249. the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
  250. */
  251. }
  252. /**
  253. * @brief DeInitializes TIM Hall Sensor MSP.
  254. * @param htim TIM Hall Sensor Interface handle
  255. * @retval None
  256. */
  257. __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
  258. {
  259. /* Prevent unused argument(s) compilation warning */
  260. UNUSED(htim);
  261. /* NOTE : This function should not be modified, when the callback is needed,
  262. the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
  263. */
  264. }
  265. /**
  266. * @brief Starts the TIM Hall Sensor Interface.
  267. * @param htim TIM Hall Sensor Interface handle
  268. * @retval HAL status
  269. */
  270. HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
  271. {
  272. uint32_t tmpsmcr;
  273. HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  274. HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  275. HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  276. HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  277. /* Check the parameters */
  278. assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
  279. /* Check the TIM channels state */
  280. if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  281. || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  282. || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  283. || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  284. {
  285. return HAL_ERROR;
  286. }
  287. /* Set the TIM channels state */
  288. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  289. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  290. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  291. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  292. /* Enable the Input Capture channel 1
  293. (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
  294. TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  295. TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  296. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  297. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  298. {
  299. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  300. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  301. {
  302. __HAL_TIM_ENABLE(htim);
  303. }
  304. }
  305. else
  306. {
  307. __HAL_TIM_ENABLE(htim);
  308. }
  309. /* Return function status */
  310. return HAL_OK;
  311. }
  312. /**
  313. * @brief Stops the TIM Hall sensor Interface.
  314. * @param htim TIM Hall Sensor Interface handle
  315. * @retval HAL status
  316. */
  317. HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
  318. {
  319. /* Check the parameters */
  320. assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
  321. /* Disable the Input Capture channels 1, 2 and 3
  322. (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
  323. TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  324. TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  325. /* Disable the Peripheral */
  326. __HAL_TIM_DISABLE(htim);
  327. /* Set the TIM channels state */
  328. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  329. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  330. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  331. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  332. /* Return function status */
  333. return HAL_OK;
  334. }
  335. /**
  336. * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
  337. * @param htim TIM Hall Sensor Interface handle
  338. * @retval HAL status
  339. */
  340. HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
  341. {
  342. uint32_t tmpsmcr;
  343. HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  344. HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  345. HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  346. HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  347. /* Check the parameters */
  348. assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
  349. /* Check the TIM channels state */
  350. if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  351. || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  352. || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  353. || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  354. {
  355. return HAL_ERROR;
  356. }
  357. /* Set the TIM channels state */
  358. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  359. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  360. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  361. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  362. /* Enable the capture compare Interrupts 1 event */
  363. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  364. /* Enable the Input Capture channel 1
  365. (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
  366. TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  367. TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  368. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  369. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  370. {
  371. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  372. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  373. {
  374. __HAL_TIM_ENABLE(htim);
  375. }
  376. }
  377. else
  378. {
  379. __HAL_TIM_ENABLE(htim);
  380. }
  381. /* Return function status */
  382. return HAL_OK;
  383. }
  384. /**
  385. * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
  386. * @param htim TIM Hall Sensor Interface handle
  387. * @retval HAL status
  388. */
  389. HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
  390. {
  391. /* Check the parameters */
  392. assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
  393. /* Disable the Input Capture channel 1
  394. (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
  395. TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  396. TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  397. /* Disable the capture compare Interrupts event */
  398. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  399. /* Disable the Peripheral */
  400. __HAL_TIM_DISABLE(htim);
  401. /* Set the TIM channels state */
  402. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  403. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  404. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  405. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  406. /* Return function status */
  407. return HAL_OK;
  408. }
  409. /**
  410. * @brief Starts the TIM Hall Sensor Interface in DMA mode.
  411. * @param htim TIM Hall Sensor Interface handle
  412. * @param pData The destination Buffer address.
  413. * @param Length The length of data to be transferred from TIM peripheral to memory.
  414. * @retval HAL status
  415. */
  416. HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
  417. {
  418. uint32_t tmpsmcr;
  419. HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  420. HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  421. /* Check the parameters */
  422. assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
  423. /* Set the TIM channel state */
  424. if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  425. || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
  426. {
  427. return HAL_BUSY;
  428. }
  429. else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  430. && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
  431. {
  432. if ((pData == NULL) || (Length == 0U))
  433. {
  434. return HAL_ERROR;
  435. }
  436. else
  437. {
  438. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  439. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  440. }
  441. }
  442. else
  443. {
  444. return HAL_ERROR;
  445. }
  446. /* Enable the Input Capture channel 1
  447. (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
  448. TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  449. TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  450. /* Set the DMA Input Capture 1 Callbacks */
  451. htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  452. htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  453. /* Set the DMA error callback */
  454. htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  455. /* Enable the DMA channel for Capture 1*/
  456. if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
  457. {
  458. /* Return error status */
  459. return HAL_ERROR;
  460. }
  461. /* Enable the capture compare 1 Interrupt */
  462. __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  463. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  464. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  465. {
  466. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  467. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  468. {
  469. __HAL_TIM_ENABLE(htim);
  470. }
  471. }
  472. else
  473. {
  474. __HAL_TIM_ENABLE(htim);
  475. }
  476. /* Return function status */
  477. return HAL_OK;
  478. }
  479. /**
  480. * @brief Stops the TIM Hall Sensor Interface in DMA mode.
  481. * @param htim TIM Hall Sensor Interface handle
  482. * @retval HAL status
  483. */
  484. HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
  485. {
  486. /* Check the parameters */
  487. assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
  488. /* Disable the Input Capture channel 1
  489. (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
  490. TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  491. TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  492. /* Disable the capture compare Interrupts 1 event */
  493. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  494. (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  495. /* Disable the Peripheral */
  496. __HAL_TIM_DISABLE(htim);
  497. /* Set the TIM channel state */
  498. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  499. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  500. /* Return function status */
  501. return HAL_OK;
  502. }
  503. /**
  504. * @}
  505. */
  506. /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
  507. * @brief Timer Complementary Output Compare functions
  508. *
  509. @verbatim
  510. ==============================================================================
  511. ##### Timer Complementary Output Compare functions #####
  512. ==============================================================================
  513. [..]
  514. This section provides functions allowing to:
  515. (+) Start the Complementary Output Compare/PWM.
  516. (+) Stop the Complementary Output Compare/PWM.
  517. (+) Start the Complementary Output Compare/PWM and enable interrupts.
  518. (+) Stop the Complementary Output Compare/PWM and disable interrupts.
  519. (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
  520. (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
  521. @endverbatim
  522. * @{
  523. */
  524. /**
  525. * @brief Starts the TIM Output Compare signal generation on the complementary
  526. * output.
  527. * @param htim TIM Output Compare handle
  528. * @param Channel TIM Channel to be enabled
  529. * This parameter can be one of the following values:
  530. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  531. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  532. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  533. * @retval HAL status
  534. */
  535. HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  536. {
  537. uint32_t tmpsmcr;
  538. /* Check the parameters */
  539. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  540. /* Check the TIM complementary channel state */
  541. if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  542. {
  543. return HAL_ERROR;
  544. }
  545. /* Set the TIM complementary channel state */
  546. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  547. /* Enable the Capture compare channel N */
  548. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
  549. /* Enable the Main Output */
  550. __HAL_TIM_MOE_ENABLE(htim);
  551. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  552. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  553. {
  554. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  555. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  556. {
  557. __HAL_TIM_ENABLE(htim);
  558. }
  559. }
  560. else
  561. {
  562. __HAL_TIM_ENABLE(htim);
  563. }
  564. /* Return function status */
  565. return HAL_OK;
  566. }
  567. /**
  568. * @brief Stops the TIM Output Compare signal generation on the complementary
  569. * output.
  570. * @param htim TIM handle
  571. * @param Channel TIM Channel to be disabled
  572. * This parameter can be one of the following values:
  573. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  574. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  575. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  576. * @retval HAL status
  577. */
  578. HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  579. {
  580. /* Check the parameters */
  581. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  582. /* Disable the Capture compare channel N */
  583. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
  584. /* Disable the Main Output */
  585. __HAL_TIM_MOE_DISABLE(htim);
  586. /* Disable the Peripheral */
  587. __HAL_TIM_DISABLE(htim);
  588. /* Set the TIM complementary channel state */
  589. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  590. /* Return function status */
  591. return HAL_OK;
  592. }
  593. /**
  594. * @brief Starts the TIM Output Compare signal generation in interrupt mode
  595. * on the complementary output.
  596. * @param htim TIM OC handle
  597. * @param Channel TIM Channel to be enabled
  598. * This parameter can be one of the following values:
  599. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  600. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  601. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  602. * @retval HAL status
  603. */
  604. HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  605. {
  606. HAL_StatusTypeDef status = HAL_OK;
  607. uint32_t tmpsmcr;
  608. /* Check the parameters */
  609. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  610. /* Check the TIM complementary channel state */
  611. if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  612. {
  613. return HAL_ERROR;
  614. }
  615. /* Set the TIM complementary channel state */
  616. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  617. switch (Channel)
  618. {
  619. case TIM_CHANNEL_1:
  620. {
  621. /* Enable the TIM Output Compare interrupt */
  622. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  623. break;
  624. }
  625. case TIM_CHANNEL_2:
  626. {
  627. /* Enable the TIM Output Compare interrupt */
  628. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  629. break;
  630. }
  631. case TIM_CHANNEL_3:
  632. {
  633. /* Enable the TIM Output Compare interrupt */
  634. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  635. break;
  636. }
  637. default:
  638. status = HAL_ERROR;
  639. break;
  640. }
  641. if (status == HAL_OK)
  642. {
  643. /* Enable the TIM Break interrupt */
  644. __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
  645. /* Enable the Capture compare channel N */
  646. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
  647. /* Enable the Main Output */
  648. __HAL_TIM_MOE_ENABLE(htim);
  649. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  650. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  651. {
  652. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  653. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  654. {
  655. __HAL_TIM_ENABLE(htim);
  656. }
  657. }
  658. else
  659. {
  660. __HAL_TIM_ENABLE(htim);
  661. }
  662. }
  663. /* Return function status */
  664. return status;
  665. }
  666. /**
  667. * @brief Stops the TIM Output Compare signal generation in interrupt mode
  668. * on the complementary output.
  669. * @param htim TIM Output Compare handle
  670. * @param Channel TIM Channel to be disabled
  671. * This parameter can be one of the following values:
  672. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  673. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  674. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  675. * @retval HAL status
  676. */
  677. HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  678. {
  679. HAL_StatusTypeDef status = HAL_OK;
  680. uint32_t tmpccer;
  681. /* Check the parameters */
  682. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  683. switch (Channel)
  684. {
  685. case TIM_CHANNEL_1:
  686. {
  687. /* Disable the TIM Output Compare interrupt */
  688. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  689. break;
  690. }
  691. case TIM_CHANNEL_2:
  692. {
  693. /* Disable the TIM Output Compare interrupt */
  694. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  695. break;
  696. }
  697. case TIM_CHANNEL_3:
  698. {
  699. /* Disable the TIM Output Compare interrupt */
  700. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  701. break;
  702. }
  703. default:
  704. status = HAL_ERROR;
  705. break;
  706. }
  707. if (status == HAL_OK)
  708. {
  709. /* Disable the Capture compare channel N */
  710. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
  711. /* Disable the TIM Break interrupt (only if no more channel is active) */
  712. tmpccer = htim->Instance->CCER;
  713. if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
  714. {
  715. __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
  716. }
  717. /* Disable the Main Output */
  718. __HAL_TIM_MOE_DISABLE(htim);
  719. /* Disable the Peripheral */
  720. __HAL_TIM_DISABLE(htim);
  721. /* Set the TIM complementary channel state */
  722. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  723. }
  724. /* Return function status */
  725. return status;
  726. }
  727. /**
  728. * @brief Starts the TIM Output Compare signal generation in DMA mode
  729. * on the complementary output.
  730. * @param htim TIM Output Compare handle
  731. * @param Channel TIM Channel to be enabled
  732. * This parameter can be one of the following values:
  733. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  734. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  735. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  736. * @param pData The source Buffer address.
  737. * @param Length The length of data to be transferred from memory to TIM peripheral
  738. * @retval HAL status
  739. */
  740. HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
  741. uint16_t Length)
  742. {
  743. HAL_StatusTypeDef status = HAL_OK;
  744. uint32_t tmpsmcr;
  745. /* Check the parameters */
  746. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  747. /* Set the TIM complementary channel state */
  748. if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  749. {
  750. return HAL_BUSY;
  751. }
  752. else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  753. {
  754. if ((pData == NULL) || (Length == 0U))
  755. {
  756. return HAL_ERROR;
  757. }
  758. else
  759. {
  760. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  761. }
  762. }
  763. else
  764. {
  765. return HAL_ERROR;
  766. }
  767. switch (Channel)
  768. {
  769. case TIM_CHANNEL_1:
  770. {
  771. /* Set the DMA compare callbacks */
  772. htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
  773. htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  774. /* Set the DMA error callback */
  775. htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
  776. /* Enable the DMA channel */
  777. if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
  778. Length) != HAL_OK)
  779. {
  780. /* Return error status */
  781. return HAL_ERROR;
  782. }
  783. /* Enable the TIM Output Compare DMA request */
  784. __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  785. break;
  786. }
  787. case TIM_CHANNEL_2:
  788. {
  789. /* Set the DMA compare callbacks */
  790. htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
  791. htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  792. /* Set the DMA error callback */
  793. htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
  794. /* Enable the DMA channel */
  795. if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
  796. Length) != HAL_OK)
  797. {
  798. /* Return error status */
  799. return HAL_ERROR;
  800. }
  801. /* Enable the TIM Output Compare DMA request */
  802. __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  803. break;
  804. }
  805. case TIM_CHANNEL_3:
  806. {
  807. /* Set the DMA compare callbacks */
  808. htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
  809. htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  810. /* Set the DMA error callback */
  811. htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
  812. /* Enable the DMA channel */
  813. if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
  814. Length) != HAL_OK)
  815. {
  816. /* Return error status */
  817. return HAL_ERROR;
  818. }
  819. /* Enable the TIM Output Compare DMA request */
  820. __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  821. break;
  822. }
  823. default:
  824. status = HAL_ERROR;
  825. break;
  826. }
  827. if (status == HAL_OK)
  828. {
  829. /* Enable the Capture compare channel N */
  830. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
  831. /* Enable the Main Output */
  832. __HAL_TIM_MOE_ENABLE(htim);
  833. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  834. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  835. {
  836. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  837. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  838. {
  839. __HAL_TIM_ENABLE(htim);
  840. }
  841. }
  842. else
  843. {
  844. __HAL_TIM_ENABLE(htim);
  845. }
  846. }
  847. /* Return function status */
  848. return status;
  849. }
  850. /**
  851. * @brief Stops the TIM Output Compare signal generation in DMA mode
  852. * on the complementary output.
  853. * @param htim TIM Output Compare handle
  854. * @param Channel TIM Channel to be disabled
  855. * This parameter can be one of the following values:
  856. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  857. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  858. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  859. * @retval HAL status
  860. */
  861. HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  862. {
  863. HAL_StatusTypeDef status = HAL_OK;
  864. /* Check the parameters */
  865. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  866. switch (Channel)
  867. {
  868. case TIM_CHANNEL_1:
  869. {
  870. /* Disable the TIM Output Compare DMA request */
  871. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  872. (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  873. break;
  874. }
  875. case TIM_CHANNEL_2:
  876. {
  877. /* Disable the TIM Output Compare DMA request */
  878. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  879. (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  880. break;
  881. }
  882. case TIM_CHANNEL_3:
  883. {
  884. /* Disable the TIM Output Compare DMA request */
  885. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  886. (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  887. break;
  888. }
  889. default:
  890. status = HAL_ERROR;
  891. break;
  892. }
  893. if (status == HAL_OK)
  894. {
  895. /* Disable the Capture compare channel N */
  896. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
  897. /* Disable the Main Output */
  898. __HAL_TIM_MOE_DISABLE(htim);
  899. /* Disable the Peripheral */
  900. __HAL_TIM_DISABLE(htim);
  901. /* Set the TIM complementary channel state */
  902. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  903. }
  904. /* Return function status */
  905. return status;
  906. }
  907. /**
  908. * @}
  909. */
  910. /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
  911. * @brief Timer Complementary PWM functions
  912. *
  913. @verbatim
  914. ==============================================================================
  915. ##### Timer Complementary PWM functions #####
  916. ==============================================================================
  917. [..]
  918. This section provides functions allowing to:
  919. (+) Start the Complementary PWM.
  920. (+) Stop the Complementary PWM.
  921. (+) Start the Complementary PWM and enable interrupts.
  922. (+) Stop the Complementary PWM and disable interrupts.
  923. (+) Start the Complementary PWM and enable DMA transfers.
  924. (+) Stop the Complementary PWM and disable DMA transfers.
  925. @endverbatim
  926. * @{
  927. */
  928. /**
  929. * @brief Starts the PWM signal generation on the complementary output.
  930. * @param htim TIM handle
  931. * @param Channel TIM Channel to be enabled
  932. * This parameter can be one of the following values:
  933. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  934. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  935. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  936. * @retval HAL status
  937. */
  938. HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  939. {
  940. uint32_t tmpsmcr;
  941. /* Check the parameters */
  942. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  943. /* Check the TIM complementary channel state */
  944. if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  945. {
  946. return HAL_ERROR;
  947. }
  948. /* Set the TIM complementary channel state */
  949. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  950. /* Enable the complementary PWM output */
  951. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
  952. /* Enable the Main Output */
  953. __HAL_TIM_MOE_ENABLE(htim);
  954. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  955. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  956. {
  957. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  958. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  959. {
  960. __HAL_TIM_ENABLE(htim);
  961. }
  962. }
  963. else
  964. {
  965. __HAL_TIM_ENABLE(htim);
  966. }
  967. /* Return function status */
  968. return HAL_OK;
  969. }
  970. /**
  971. * @brief Stops the PWM signal generation on the complementary output.
  972. * @param htim TIM handle
  973. * @param Channel TIM Channel to be disabled
  974. * This parameter can be one of the following values:
  975. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  976. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  977. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  978. * @retval HAL status
  979. */
  980. HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  981. {
  982. /* Check the parameters */
  983. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  984. /* Disable the complementary PWM output */
  985. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
  986. /* Disable the Main Output */
  987. __HAL_TIM_MOE_DISABLE(htim);
  988. /* Disable the Peripheral */
  989. __HAL_TIM_DISABLE(htim);
  990. /* Set the TIM complementary channel state */
  991. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  992. /* Return function status */
  993. return HAL_OK;
  994. }
  995. /**
  996. * @brief Starts the PWM signal generation in interrupt mode on the
  997. * complementary output.
  998. * @param htim TIM handle
  999. * @param Channel TIM Channel to be disabled
  1000. * This parameter can be one of the following values:
  1001. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1002. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1003. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1004. * @retval HAL status
  1005. */
  1006. HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1007. {
  1008. HAL_StatusTypeDef status = HAL_OK;
  1009. uint32_t tmpsmcr;
  1010. /* Check the parameters */
  1011. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  1012. /* Check the TIM complementary channel state */
  1013. if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1014. {
  1015. return HAL_ERROR;
  1016. }
  1017. /* Set the TIM complementary channel state */
  1018. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1019. switch (Channel)
  1020. {
  1021. case TIM_CHANNEL_1:
  1022. {
  1023. /* Enable the TIM Capture/Compare 1 interrupt */
  1024. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  1025. break;
  1026. }
  1027. case TIM_CHANNEL_2:
  1028. {
  1029. /* Enable the TIM Capture/Compare 2 interrupt */
  1030. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  1031. break;
  1032. }
  1033. case TIM_CHANNEL_3:
  1034. {
  1035. /* Enable the TIM Capture/Compare 3 interrupt */
  1036. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  1037. break;
  1038. }
  1039. default:
  1040. status = HAL_ERROR;
  1041. break;
  1042. }
  1043. if (status == HAL_OK)
  1044. {
  1045. /* Enable the TIM Break interrupt */
  1046. __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
  1047. /* Enable the complementary PWM output */
  1048. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
  1049. /* Enable the Main Output */
  1050. __HAL_TIM_MOE_ENABLE(htim);
  1051. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1052. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1053. {
  1054. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1055. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1056. {
  1057. __HAL_TIM_ENABLE(htim);
  1058. }
  1059. }
  1060. else
  1061. {
  1062. __HAL_TIM_ENABLE(htim);
  1063. }
  1064. }
  1065. /* Return function status */
  1066. return status;
  1067. }
  1068. /**
  1069. * @brief Stops the PWM signal generation in interrupt mode on the
  1070. * complementary output.
  1071. * @param htim TIM handle
  1072. * @param Channel TIM Channel to be disabled
  1073. * This parameter can be one of the following values:
  1074. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1075. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1076. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1077. * @retval HAL status
  1078. */
  1079. HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1080. {
  1081. HAL_StatusTypeDef status = HAL_OK;
  1082. uint32_t tmpccer;
  1083. /* Check the parameters */
  1084. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  1085. switch (Channel)
  1086. {
  1087. case TIM_CHANNEL_1:
  1088. {
  1089. /* Disable the TIM Capture/Compare 1 interrupt */
  1090. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  1091. break;
  1092. }
  1093. case TIM_CHANNEL_2:
  1094. {
  1095. /* Disable the TIM Capture/Compare 2 interrupt */
  1096. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  1097. break;
  1098. }
  1099. case TIM_CHANNEL_3:
  1100. {
  1101. /* Disable the TIM Capture/Compare 3 interrupt */
  1102. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  1103. break;
  1104. }
  1105. default:
  1106. status = HAL_ERROR;
  1107. break;
  1108. }
  1109. if (status == HAL_OK)
  1110. {
  1111. /* Disable the complementary PWM output */
  1112. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
  1113. /* Disable the TIM Break interrupt (only if no more channel is active) */
  1114. tmpccer = htim->Instance->CCER;
  1115. if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
  1116. {
  1117. __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
  1118. }
  1119. /* Disable the Main Output */
  1120. __HAL_TIM_MOE_DISABLE(htim);
  1121. /* Disable the Peripheral */
  1122. __HAL_TIM_DISABLE(htim);
  1123. /* Set the TIM complementary channel state */
  1124. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1125. }
  1126. /* Return function status */
  1127. return status;
  1128. }
  1129. /**
  1130. * @brief Starts the TIM PWM signal generation in DMA mode on the
  1131. * complementary output
  1132. * @param htim TIM handle
  1133. * @param Channel TIM Channel to be enabled
  1134. * This parameter can be one of the following values:
  1135. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1136. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1137. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1138. * @param pData The source Buffer address.
  1139. * @param Length The length of data to be transferred from memory to TIM peripheral
  1140. * @retval HAL status
  1141. */
  1142. HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
  1143. uint16_t Length)
  1144. {
  1145. HAL_StatusTypeDef status = HAL_OK;
  1146. uint32_t tmpsmcr;
  1147. /* Check the parameters */
  1148. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  1149. /* Set the TIM complementary channel state */
  1150. if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1151. {
  1152. return HAL_BUSY;
  1153. }
  1154. else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1155. {
  1156. if ((pData == NULL) || (Length == 0U))
  1157. {
  1158. return HAL_ERROR;
  1159. }
  1160. else
  1161. {
  1162. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1163. }
  1164. }
  1165. else
  1166. {
  1167. return HAL_ERROR;
  1168. }
  1169. switch (Channel)
  1170. {
  1171. case TIM_CHANNEL_1:
  1172. {
  1173. /* Set the DMA compare callbacks */
  1174. htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
  1175. htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1176. /* Set the DMA error callback */
  1177. htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
  1178. /* Enable the DMA channel */
  1179. if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
  1180. Length) != HAL_OK)
  1181. {
  1182. /* Return error status */
  1183. return HAL_ERROR;
  1184. }
  1185. /* Enable the TIM Capture/Compare 1 DMA request */
  1186. __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1187. break;
  1188. }
  1189. case TIM_CHANNEL_2:
  1190. {
  1191. /* Set the DMA compare callbacks */
  1192. htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
  1193. htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1194. /* Set the DMA error callback */
  1195. htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
  1196. /* Enable the DMA channel */
  1197. if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
  1198. Length) != HAL_OK)
  1199. {
  1200. /* Return error status */
  1201. return HAL_ERROR;
  1202. }
  1203. /* Enable the TIM Capture/Compare 2 DMA request */
  1204. __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1205. break;
  1206. }
  1207. case TIM_CHANNEL_3:
  1208. {
  1209. /* Set the DMA compare callbacks */
  1210. htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
  1211. htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1212. /* Set the DMA error callback */
  1213. htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
  1214. /* Enable the DMA channel */
  1215. if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
  1216. Length) != HAL_OK)
  1217. {
  1218. /* Return error status */
  1219. return HAL_ERROR;
  1220. }
  1221. /* Enable the TIM Capture/Compare 3 DMA request */
  1222. __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1223. break;
  1224. }
  1225. default:
  1226. status = HAL_ERROR;
  1227. break;
  1228. }
  1229. if (status == HAL_OK)
  1230. {
  1231. /* Enable the complementary PWM output */
  1232. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
  1233. /* Enable the Main Output */
  1234. __HAL_TIM_MOE_ENABLE(htim);
  1235. /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1236. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1237. {
  1238. tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1239. if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1240. {
  1241. __HAL_TIM_ENABLE(htim);
  1242. }
  1243. }
  1244. else
  1245. {
  1246. __HAL_TIM_ENABLE(htim);
  1247. }
  1248. }
  1249. /* Return function status */
  1250. return status;
  1251. }
  1252. /**
  1253. * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
  1254. * output
  1255. * @param htim TIM handle
  1256. * @param Channel TIM Channel to be disabled
  1257. * This parameter can be one of the following values:
  1258. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1259. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1260. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1261. * @retval HAL status
  1262. */
  1263. HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1264. {
  1265. HAL_StatusTypeDef status = HAL_OK;
  1266. /* Check the parameters */
  1267. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
  1268. switch (Channel)
  1269. {
  1270. case TIM_CHANNEL_1:
  1271. {
  1272. /* Disable the TIM Capture/Compare 1 DMA request */
  1273. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1274. (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1275. break;
  1276. }
  1277. case TIM_CHANNEL_2:
  1278. {
  1279. /* Disable the TIM Capture/Compare 2 DMA request */
  1280. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1281. (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1282. break;
  1283. }
  1284. case TIM_CHANNEL_3:
  1285. {
  1286. /* Disable the TIM Capture/Compare 3 DMA request */
  1287. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1288. (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1289. break;
  1290. }
  1291. default:
  1292. status = HAL_ERROR;
  1293. break;
  1294. }
  1295. if (status == HAL_OK)
  1296. {
  1297. /* Disable the complementary PWM output */
  1298. TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
  1299. /* Disable the Main Output */
  1300. __HAL_TIM_MOE_DISABLE(htim);
  1301. /* Disable the Peripheral */
  1302. __HAL_TIM_DISABLE(htim);
  1303. /* Set the TIM complementary channel state */
  1304. TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1305. }
  1306. /* Return function status */
  1307. return status;
  1308. }
  1309. /**
  1310. * @}
  1311. */
  1312. /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
  1313. * @brief Timer Complementary One Pulse functions
  1314. *
  1315. @verbatim
  1316. ==============================================================================
  1317. ##### Timer Complementary One Pulse functions #####
  1318. ==============================================================================
  1319. [..]
  1320. This section provides functions allowing to:
  1321. (+) Start the Complementary One Pulse generation.
  1322. (+) Stop the Complementary One Pulse.
  1323. (+) Start the Complementary One Pulse and enable interrupts.
  1324. (+) Stop the Complementary One Pulse and disable interrupts.
  1325. @endverbatim
  1326. * @{
  1327. */
  1328. /**
  1329. * @brief Starts the TIM One Pulse signal generation on the complementary
  1330. * output.
  1331. * @note OutputChannel must match the pulse output channel chosen when calling
  1332. * @ref HAL_TIM_OnePulse_ConfigChannel().
  1333. * @param htim TIM One Pulse handle
  1334. * @param OutputChannel pulse output channel to enable
  1335. * This parameter can be one of the following values:
  1336. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1337. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1338. * @retval HAL status
  1339. */
  1340. HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  1341. {
  1342. uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
  1343. HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  1344. HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  1345. HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  1346. HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  1347. /* Check the parameters */
  1348. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
  1349. /* Check the TIM channels state */
  1350. if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  1351. || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  1352. || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  1353. || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  1354. {
  1355. return HAL_ERROR;
  1356. }
  1357. /* Set the TIM channels state */
  1358. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  1359. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  1360. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  1361. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  1362. /* Enable the complementary One Pulse output channel and the Input Capture channel */
  1363. TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
  1364. TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
  1365. /* Enable the Main Output */
  1366. __HAL_TIM_MOE_ENABLE(htim);
  1367. /* Return function status */
  1368. return HAL_OK;
  1369. }
  1370. /**
  1371. * @brief Stops the TIM One Pulse signal generation on the complementary
  1372. * output.
  1373. * @note OutputChannel must match the pulse output channel chosen when calling
  1374. * @ref HAL_TIM_OnePulse_ConfigChannel().
  1375. * @param htim TIM One Pulse handle
  1376. * @param OutputChannel pulse output channel to disable
  1377. * This parameter can be one of the following values:
  1378. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1379. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1380. * @retval HAL status
  1381. */
  1382. HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  1383. {
  1384. uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
  1385. /* Check the parameters */
  1386. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
  1387. /* Disable the complementary One Pulse output channel and the Input Capture channel */
  1388. TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
  1389. TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
  1390. /* Disable the Main Output */
  1391. __HAL_TIM_MOE_DISABLE(htim);
  1392. /* Disable the Peripheral */
  1393. __HAL_TIM_DISABLE(htim);
  1394. /* Set the TIM channels state */
  1395. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  1396. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  1397. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  1398. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  1399. /* Return function status */
  1400. return HAL_OK;
  1401. }
  1402. /**
  1403. * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
  1404. * complementary channel.
  1405. * @note OutputChannel must match the pulse output channel chosen when calling
  1406. * @ref HAL_TIM_OnePulse_ConfigChannel().
  1407. * @param htim TIM One Pulse handle
  1408. * @param OutputChannel pulse output channel to enable
  1409. * This parameter can be one of the following values:
  1410. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1411. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1412. * @retval HAL status
  1413. */
  1414. HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  1415. {
  1416. uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
  1417. HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  1418. HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  1419. HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  1420. HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  1421. /* Check the parameters */
  1422. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
  1423. /* Check the TIM channels state */
  1424. if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  1425. || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  1426. || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  1427. || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  1428. {
  1429. return HAL_ERROR;
  1430. }
  1431. /* Set the TIM channels state */
  1432. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  1433. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  1434. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  1435. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  1436. /* Enable the TIM Capture/Compare 1 interrupt */
  1437. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  1438. /* Enable the TIM Capture/Compare 2 interrupt */
  1439. __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  1440. /* Enable the complementary One Pulse output channel and the Input Capture channel */
  1441. TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
  1442. TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
  1443. /* Enable the Main Output */
  1444. __HAL_TIM_MOE_ENABLE(htim);
  1445. /* Return function status */
  1446. return HAL_OK;
  1447. }
  1448. /**
  1449. * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
  1450. * complementary channel.
  1451. * @note OutputChannel must match the pulse output channel chosen when calling
  1452. * @ref HAL_TIM_OnePulse_ConfigChannel().
  1453. * @param htim TIM One Pulse handle
  1454. * @param OutputChannel pulse output channel to disable
  1455. * This parameter can be one of the following values:
  1456. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1457. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1458. * @retval HAL status
  1459. */
  1460. HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  1461. {
  1462. uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
  1463. /* Check the parameters */
  1464. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
  1465. /* Disable the TIM Capture/Compare 1 interrupt */
  1466. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  1467. /* Disable the TIM Capture/Compare 2 interrupt */
  1468. __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  1469. /* Disable the complementary One Pulse output channel and the Input Capture channel */
  1470. TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
  1471. TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
  1472. /* Disable the Main Output */
  1473. __HAL_TIM_MOE_DISABLE(htim);
  1474. /* Disable the Peripheral */
  1475. __HAL_TIM_DISABLE(htim);
  1476. /* Set the TIM channels state */
  1477. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  1478. TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  1479. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  1480. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  1481. /* Return function status */
  1482. return HAL_OK;
  1483. }
  1484. /**
  1485. * @}
  1486. */
  1487. /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
  1488. * @brief Peripheral Control functions
  1489. *
  1490. @verbatim
  1491. ==============================================================================
  1492. ##### Peripheral Control functions #####
  1493. ==============================================================================
  1494. [..]
  1495. This section provides functions allowing to:
  1496. (+) Configure the commutation event in case of use of the Hall sensor interface.
  1497. (+) Configure Output channels for OC and PWM mode.
  1498. (+) Configure Complementary channels, break features and dead time.
  1499. (+) Configure Master synchronization.
  1500. (+) Configure timer remapping capabilities.
  1501. (+) Enable or disable channel grouping.
  1502. @endverbatim
  1503. * @{
  1504. */
  1505. /**
  1506. * @brief Configure the TIM commutation event sequence.
  1507. * @note This function is mandatory to use the commutation event in order to
  1508. * update the configuration at each commutation detection on the TRGI input of the Timer,
  1509. * the typical use of this feature is with the use of another Timer(interface Timer)
  1510. * configured in Hall sensor interface, this interface Timer will generate the
  1511. * commutation at its TRGO output (connected to Timer used in this function) each time
  1512. * the TI1 of the Interface Timer detect a commutation at its input TI1.
  1513. * @param htim TIM handle
  1514. * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
  1515. * This parameter can be one of the following values:
  1516. * @arg TIM_TS_ITR0: Internal trigger 0 selected
  1517. * @arg TIM_TS_ITR1: Internal trigger 1 selected
  1518. * @arg TIM_TS_ITR2: Internal trigger 2 selected
  1519. * @arg TIM_TS_ITR3: Internal trigger 3 selected
  1520. * @arg TIM_TS_NONE: No trigger is needed
  1521. * @param CommutationSource the Commutation Event source
  1522. * This parameter can be one of the following values:
  1523. * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  1524. * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
  1525. * @retval HAL status
  1526. */
  1527. HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
  1528. uint32_t CommutationSource)
  1529. {
  1530. /* Check the parameters */
  1531. assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
  1532. assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
  1533. __HAL_LOCK(htim);
  1534. if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
  1535. (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
  1536. {
  1537. /* Select the Input trigger */
  1538. htim->Instance->SMCR &= ~TIM_SMCR_TS;
  1539. htim->Instance->SMCR |= InputTrigger;
  1540. }
  1541. /* Select the Capture Compare preload feature */
  1542. htim->Instance->CR2 |= TIM_CR2_CCPC;
  1543. /* Select the Commutation event source */
  1544. htim->Instance->CR2 &= ~TIM_CR2_CCUS;
  1545. htim->Instance->CR2 |= CommutationSource;
  1546. /* Disable Commutation Interrupt */
  1547. __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
  1548. /* Disable Commutation DMA request */
  1549. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
  1550. __HAL_UNLOCK(htim);
  1551. return HAL_OK;
  1552. }
  1553. /**
  1554. * @brief Configure the TIM commutation event sequence with interrupt.
  1555. * @note This function is mandatory to use the commutation event in order to
  1556. * update the configuration at each commutation detection on the TRGI input of the Timer,
  1557. * the typical use of this feature is with the use of another Timer(interface Timer)
  1558. * configured in Hall sensor interface, this interface Timer will generate the
  1559. * commutation at its TRGO output (connected to Timer used in this function) each time
  1560. * the TI1 of the Interface Timer detect a commutation at its input TI1.
  1561. * @param htim TIM handle
  1562. * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
  1563. * This parameter can be one of the following values:
  1564. * @arg TIM_TS_ITR0: Internal trigger 0 selected
  1565. * @arg TIM_TS_ITR1: Internal trigger 1 selected
  1566. * @arg TIM_TS_ITR2: Internal trigger 2 selected
  1567. * @arg TIM_TS_ITR3: Internal trigger 3 selected
  1568. * @arg TIM_TS_NONE: No trigger is needed
  1569. * @param CommutationSource the Commutation Event source
  1570. * This parameter can be one of the following values:
  1571. * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  1572. * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
  1573. * @retval HAL status
  1574. */
  1575. HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
  1576. uint32_t CommutationSource)
  1577. {
  1578. /* Check the parameters */
  1579. assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
  1580. assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
  1581. __HAL_LOCK(htim);
  1582. if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
  1583. (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
  1584. {
  1585. /* Select the Input trigger */
  1586. htim->Instance->SMCR &= ~TIM_SMCR_TS;
  1587. htim->Instance->SMCR |= InputTrigger;
  1588. }
  1589. /* Select the Capture Compare preload feature */
  1590. htim->Instance->CR2 |= TIM_CR2_CCPC;
  1591. /* Select the Commutation event source */
  1592. htim->Instance->CR2 &= ~TIM_CR2_CCUS;
  1593. htim->Instance->CR2 |= CommutationSource;
  1594. /* Disable Commutation DMA request */
  1595. __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
  1596. /* Enable the Commutation Interrupt */
  1597. __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
  1598. __HAL_UNLOCK(htim);
  1599. return HAL_OK;
  1600. }
  1601. /**
  1602. * @brief Configure the TIM commutation event sequence with DMA.
  1603. * @note This function is mandatory to use the commutation event in order to
  1604. * update the configuration at each commutation detection on the TRGI input of the Timer,
  1605. * the typical use of this feature is with the use of another Timer(interface Timer)
  1606. * configured in Hall sensor interface, this interface Timer will generate the
  1607. * commutation at its TRGO output (connected to Timer used in this function) each time
  1608. * the TI1 of the Interface Timer detect a commutation at its input TI1.
  1609. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
  1610. * @param htim TIM handle
  1611. * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
  1612. * This parameter can be one of the following values:
  1613. * @arg TIM_TS_ITR0: Internal trigger 0 selected
  1614. * @arg TIM_TS_ITR1: Internal trigger 1 selected
  1615. * @arg TIM_TS_ITR2: Internal trigger 2 selected
  1616. * @arg TIM_TS_ITR3: Internal trigger 3 selected
  1617. * @arg TIM_TS_NONE: No trigger is needed
  1618. * @param CommutationSource the Commutation Event source
  1619. * This parameter can be one of the following values:
  1620. * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  1621. * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
  1622. * @retval HAL status
  1623. */
  1624. HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
  1625. uint32_t CommutationSource)
  1626. {
  1627. /* Check the parameters */
  1628. assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
  1629. assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
  1630. __HAL_LOCK(htim);
  1631. if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
  1632. (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
  1633. {
  1634. /* Select the Input trigger */
  1635. htim->Instance->SMCR &= ~TIM_SMCR_TS;
  1636. htim->Instance->SMCR |= InputTrigger;
  1637. }
  1638. /* Select the Capture Compare preload feature */
  1639. htim->Instance->CR2 |= TIM_CR2_CCPC;
  1640. /* Select the Commutation event source */
  1641. htim->Instance->CR2 &= ~TIM_CR2_CCUS;
  1642. htim->Instance->CR2 |= CommutationSource;
  1643. /* Enable the Commutation DMA Request */
  1644. /* Set the DMA Commutation Callback */
  1645. htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
  1646. htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
  1647. /* Set the DMA error callback */
  1648. htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
  1649. /* Disable Commutation Interrupt */
  1650. __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
  1651. /* Enable the Commutation DMA Request */
  1652. __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
  1653. __HAL_UNLOCK(htim);
  1654. return HAL_OK;
  1655. }
  1656. /**
  1657. * @brief Configures the TIM in master mode.
  1658. * @param htim TIM handle.
  1659. * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
  1660. * contains the selected trigger output (TRGO) and the Master/Slave
  1661. * mode.
  1662. * @retval HAL status
  1663. */
  1664. HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
  1665. const TIM_MasterConfigTypeDef *sMasterConfig)
  1666. {
  1667. uint32_t tmpcr2;
  1668. uint32_t tmpsmcr;
  1669. /* Check the parameters */
  1670. assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  1671. assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  1672. assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
  1673. /* Check input state */
  1674. __HAL_LOCK(htim);
  1675. /* Change the handler state */
  1676. htim->State = HAL_TIM_STATE_BUSY;
  1677. /* Get the TIMx CR2 register value */
  1678. tmpcr2 = htim->Instance->CR2;
  1679. /* Get the TIMx SMCR register value */
  1680. tmpsmcr = htim->Instance->SMCR;
  1681. #if defined(TIM_CR2_MMS2)
  1682. /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
  1683. if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
  1684. {
  1685. /* Check the parameters */
  1686. assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
  1687. /* Clear the MMS2 bits */
  1688. tmpcr2 &= ~TIM_CR2_MMS2;
  1689. /* Select the TRGO2 source*/
  1690. tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
  1691. }
  1692. #endif /* TIM_CR2_MMS2 */
  1693. /* Reset the MMS Bits */
  1694. tmpcr2 &= ~TIM_CR2_MMS;
  1695. /* Select the TRGO source */
  1696. tmpcr2 |= sMasterConfig->MasterOutputTrigger;
  1697. /* Update TIMx CR2 */
  1698. htim->Instance->CR2 = tmpcr2;
  1699. if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1700. {
  1701. /* Reset the MSM Bit */
  1702. tmpsmcr &= ~TIM_SMCR_MSM;
  1703. /* Set master mode */
  1704. tmpsmcr |= sMasterConfig->MasterSlaveMode;
  1705. /* Update TIMx SMCR */
  1706. htim->Instance->SMCR = tmpsmcr;
  1707. }
  1708. /* Change the htim state */
  1709. htim->State = HAL_TIM_STATE_READY;
  1710. __HAL_UNLOCK(htim);
  1711. return HAL_OK;
  1712. }
  1713. /**
  1714. * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
  1715. * and the AOE(automatic output enable).
  1716. * @param htim TIM handle
  1717. * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
  1718. * contains the BDTR Register configuration information for the TIM peripheral.
  1719. * @note Interrupts can be generated when an active level is detected on the
  1720. * break input, the break 2 input or the system break input. Break
  1721. * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
  1722. * @retval HAL status
  1723. */
  1724. HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
  1725. const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
  1726. {
  1727. /* Keep this variable initialized to 0 as it is used to configure BDTR register */
  1728. uint32_t tmpbdtr = 0U;
  1729. /* Check the parameters */
  1730. assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
  1731. assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
  1732. assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
  1733. assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
  1734. assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
  1735. assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
  1736. assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
  1737. #if defined(TIM_BDTR_BKF)
  1738. assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
  1739. #endif /* TIM_BDTR_BKF */
  1740. assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
  1741. /* Check input state */
  1742. __HAL_LOCK(htim);
  1743. /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
  1744. the OSSI State, the dead time value and the Automatic Output Enable Bit */
  1745. /* Set the BDTR bits */
  1746. MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
  1747. MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
  1748. MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
  1749. MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
  1750. MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
  1751. MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
  1752. MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
  1753. #if defined(TIM_BDTR_BKF)
  1754. MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
  1755. #endif /* TIM_BDTR_BKF */
  1756. #if defined(TIM_BDTR_BK2E)
  1757. if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
  1758. {
  1759. /* Check the parameters */
  1760. assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
  1761. assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
  1762. assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
  1763. /* Set the BREAK2 input related BDTR bits */
  1764. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
  1765. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
  1766. MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
  1767. }
  1768. #endif /* TIM_BDTR_BK2E */
  1769. /* Set TIMx_BDTR */
  1770. htim->Instance->BDTR = tmpbdtr;
  1771. __HAL_UNLOCK(htim);
  1772. return HAL_OK;
  1773. }
  1774. /**
  1775. * @brief Configures the TIMx Remapping input capabilities.
  1776. * @param htim TIM handle.
  1777. * @param Remap specifies the TIM remapping source.
  1778. @if STM32F301x8
  1779. * For TIM1, the parameter can have the following values:
  1780. * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
  1781. * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
  1782. * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
  1783. * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2
  1784. @elseif STM32F303xE
  1785. * For TIM1, the parameter is a combination of 2 fields (field1 | field2):
  1786. *
  1787. * field1 can have the following values:
  1788. * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
  1789. * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
  1790. * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
  1791. * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2
  1792. *
  1793. * field2 can have the following values:
  1794. * @arg TIM_TIM1_ADC4_NONE : TIM1_ETR is not connected to any AWD (analog watchdog)
  1795. * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
  1796. * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
  1797. * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
  1798. @elseif STM32F334x8
  1799. * For TIM1, the parameter is a combination of 2 fields (field1 | field2):
  1800. *
  1801. * field1 can have the following values:
  1802. * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
  1803. * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
  1804. * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
  1805. * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2
  1806. *
  1807. * field2 can have the following values:
  1808. * @arg TIM_TIM1_ADC2_NONE : TIM1_ETR is not connected to any AWD (analog watchdog)
  1809. * @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
  1810. * @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
  1811. * @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3
  1812. @endif
  1813. @if STM32F303xE
  1814. * For TIM8, the parameter is a combination of 2 fields (field1 | field2):
  1815. *
  1816. * field1 can have the following values:
  1817. * @arg TIM_TIM8_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
  1818. * @arg TIM_TIM8_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
  1819. * @arg TIM_TIM8_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
  1820. * @arg TIM_TIM8_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD2
  1821. *
  1822. * field2 can have the following values:
  1823. * @arg TIM_TIM8_ADC3_NONE : TIM1_ETR is not connected to any AWD (analog watchdog)
  1824. * @arg TIM_TIM8_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
  1825. * @arg TIM_TIM8_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
  1826. * @arg TIM_TIM8_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
  1827. @endif
  1828. @if STM32F373xC
  1829. * For TIM14, the parameter can have the following values:
  1830. * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
  1831. * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
  1832. * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
  1833. * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
  1834. @else
  1835. * For TIM16, the parameter can have the following values:
  1836. * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
  1837. * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
  1838. * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
  1839. * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
  1840. @endif
  1841. @if STM32F303xE
  1842. * For TIM20, the parameter is a combination of 2 fields (field1 | field2):
  1843. *
  1844. * field1 can have the following values:
  1845. * @arg TIM_TIM20_ADC3_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
  1846. * @arg TIM_TIM20_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
  1847. * @arg TIM_TIM20_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
  1848. * @arg TIM_TIM20_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD2
  1849. *
  1850. * field2 can have the following values:
  1851. * @arg TIM_TIM20_ADC4_NONE : TIM1_ETR is not connected to any AWD (analog watchdog)
  1852. * @arg TIM_TIM20_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
  1853. * @arg TIM_TIM20_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
  1854. * @arg TIM_TIM20_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
  1855. @endif
  1856. *
  1857. * @retval HAL status
  1858. */
  1859. HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
  1860. {
  1861. /* Check parameters */
  1862. assert_param(IS_TIM_REMAP(htim->Instance, Remap));
  1863. __HAL_LOCK(htim);
  1864. /* Set the Timer remapping configuration */
  1865. WRITE_REG(htim->Instance->OR, Remap);
  1866. __HAL_UNLOCK(htim);
  1867. return HAL_OK;
  1868. }
  1869. #if defined(TIM_CCR5_CCR5)
  1870. /**
  1871. * @brief Group channel 5 and channel 1, 2 or 3
  1872. * @param htim TIM handle.
  1873. * @param Channels specifies the reference signal(s) the OC5REF is combined with.
  1874. * This parameter can be any combination of the following values:
  1875. * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
  1876. * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
  1877. * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
  1878. * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
  1879. * @retval HAL status
  1880. */
  1881. HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
  1882. {
  1883. /* Check parameters */
  1884. assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
  1885. assert_param(IS_TIM_GROUPCH5(Channels));
  1886. /* Process Locked */
  1887. __HAL_LOCK(htim);
  1888. htim->State = HAL_TIM_STATE_BUSY;
  1889. /* Clear GC5Cx bit fields */
  1890. htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
  1891. /* Set GC5Cx bit fields */
  1892. htim->Instance->CCR5 |= Channels;
  1893. /* Change the htim state */
  1894. htim->State = HAL_TIM_STATE_READY;
  1895. __HAL_UNLOCK(htim);
  1896. return HAL_OK;
  1897. }
  1898. #endif /* TIM_CCR5_CCR5 */
  1899. /**
  1900. * @}
  1901. */
  1902. /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
  1903. * @brief Extended Callbacks functions
  1904. *
  1905. @verbatim
  1906. ==============================================================================
  1907. ##### Extended Callbacks functions #####
  1908. ==============================================================================
  1909. [..]
  1910. This section provides Extended TIM callback functions:
  1911. (+) Timer Commutation callback
  1912. (+) Timer Break callback
  1913. @endverbatim
  1914. * @{
  1915. */
  1916. /**
  1917. * @brief Commutation callback in non-blocking mode
  1918. * @param htim TIM handle
  1919. * @retval None
  1920. */
  1921. __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
  1922. {
  1923. /* Prevent unused argument(s) compilation warning */
  1924. UNUSED(htim);
  1925. /* NOTE : This function should not be modified, when the callback is needed,
  1926. the HAL_TIMEx_CommutCallback could be implemented in the user file
  1927. */
  1928. }
  1929. /**
  1930. * @brief Commutation half complete callback in non-blocking mode
  1931. * @param htim TIM handle
  1932. * @retval None
  1933. */
  1934. __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
  1935. {
  1936. /* Prevent unused argument(s) compilation warning */
  1937. UNUSED(htim);
  1938. /* NOTE : This function should not be modified, when the callback is needed,
  1939. the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
  1940. */
  1941. }
  1942. /**
  1943. * @brief Break detection callback in non-blocking mode
  1944. * @param htim TIM handle
  1945. * @retval None
  1946. */
  1947. __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
  1948. {
  1949. /* Prevent unused argument(s) compilation warning */
  1950. UNUSED(htim);
  1951. /* NOTE : This function should not be modified, when the callback is needed,
  1952. the HAL_TIMEx_BreakCallback could be implemented in the user file
  1953. */
  1954. }
  1955. #if defined(TIM_BDTR_BK2E)
  1956. /**
  1957. * @brief Break2 detection callback in non blocking mode
  1958. * @param htim: TIM handle
  1959. * @retval None
  1960. */
  1961. __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
  1962. {
  1963. /* Prevent unused argument(s) compilation warning */
  1964. UNUSED(htim);
  1965. /* NOTE : This function Should not be modified, when the callback is needed,
  1966. the HAL_TIMEx_Break2Callback could be implemented in the user file
  1967. */
  1968. }
  1969. #endif /* TIM_BDTR_BK2E */
  1970. /**
  1971. * @}
  1972. */
  1973. /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
  1974. * @brief Extended Peripheral State functions
  1975. *
  1976. @verbatim
  1977. ==============================================================================
  1978. ##### Extended Peripheral State functions #####
  1979. ==============================================================================
  1980. [..]
  1981. This subsection permits to get in run-time the status of the peripheral
  1982. and the data flow.
  1983. @endverbatim
  1984. * @{
  1985. */
  1986. /**
  1987. * @brief Return the TIM Hall Sensor interface handle state.
  1988. * @param htim TIM Hall Sensor handle
  1989. * @retval HAL state
  1990. */
  1991. HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
  1992. {
  1993. return htim->State;
  1994. }
  1995. /**
  1996. * @brief Return actual state of the TIM complementary channel.
  1997. * @param htim TIM handle
  1998. * @param ChannelN TIM Complementary channel
  1999. * This parameter can be one of the following values:
  2000. * @arg TIM_CHANNEL_1: TIM Channel 1
  2001. * @arg TIM_CHANNEL_2: TIM Channel 2
  2002. * @arg TIM_CHANNEL_3: TIM Channel 3
  2003. * @retval TIM Complementary channel state
  2004. */
  2005. HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
  2006. {
  2007. HAL_TIM_ChannelStateTypeDef channel_state;
  2008. /* Check the parameters */
  2009. assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
  2010. channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
  2011. return channel_state;
  2012. }
  2013. /**
  2014. * @}
  2015. */
  2016. /**
  2017. * @}
  2018. */
  2019. /* Private functions ---------------------------------------------------------*/
  2020. /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
  2021. * @{
  2022. */
  2023. /**
  2024. * @brief TIM DMA Commutation callback.
  2025. * @param hdma pointer to DMA handle.
  2026. * @retval None
  2027. */
  2028. void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
  2029. {
  2030. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2031. /* Change the htim state */
  2032. htim->State = HAL_TIM_STATE_READY;
  2033. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2034. htim->CommutationCallback(htim);
  2035. #else
  2036. HAL_TIMEx_CommutCallback(htim);
  2037. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2038. }
  2039. /**
  2040. * @brief TIM DMA Commutation half complete callback.
  2041. * @param hdma pointer to DMA handle.
  2042. * @retval None
  2043. */
  2044. void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
  2045. {
  2046. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2047. /* Change the htim state */
  2048. htim->State = HAL_TIM_STATE_READY;
  2049. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2050. htim->CommutationHalfCpltCallback(htim);
  2051. #else
  2052. HAL_TIMEx_CommutHalfCpltCallback(htim);
  2053. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2054. }
  2055. /**
  2056. * @brief TIM DMA Delay Pulse complete callback (complementary channel).
  2057. * @param hdma pointer to DMA handle.
  2058. * @retval None
  2059. */
  2060. static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
  2061. {
  2062. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2063. if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  2064. {
  2065. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  2066. if (hdma->Init.Mode == DMA_NORMAL)
  2067. {
  2068. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2069. }
  2070. }
  2071. else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  2072. {
  2073. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  2074. if (hdma->Init.Mode == DMA_NORMAL)
  2075. {
  2076. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2077. }
  2078. }
  2079. else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  2080. {
  2081. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  2082. if (hdma->Init.Mode == DMA_NORMAL)
  2083. {
  2084. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  2085. }
  2086. }
  2087. else
  2088. {
  2089. /* nothing to do */
  2090. }
  2091. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2092. htim->PWM_PulseFinishedCallback(htim);
  2093. #else
  2094. HAL_TIM_PWM_PulseFinishedCallback(htim);
  2095. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2096. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  2097. }
  2098. /**
  2099. * @brief TIM DMA error callback (complementary channel)
  2100. * @param hdma pointer to DMA handle.
  2101. * @retval None
  2102. */
  2103. static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
  2104. {
  2105. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  2106. if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  2107. {
  2108. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  2109. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2110. }
  2111. else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  2112. {
  2113. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  2114. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2115. }
  2116. else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  2117. {
  2118. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  2119. TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  2120. }
  2121. else
  2122. {
  2123. /* nothing to do */
  2124. }
  2125. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2126. htim->ErrorCallback(htim);
  2127. #else
  2128. HAL_TIM_ErrorCallback(htim);
  2129. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2130. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  2131. }
  2132. /**
  2133. * @brief Enables or disables the TIM Capture Compare Channel xN.
  2134. * @param TIMx to select the TIM peripheral
  2135. * @param Channel specifies the TIM Channel
  2136. * This parameter can be one of the following values:
  2137. * @arg TIM_CHANNEL_1: TIM Channel 1
  2138. * @arg TIM_CHANNEL_2: TIM Channel 2
  2139. * @arg TIM_CHANNEL_3: TIM Channel 3
  2140. * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
  2141. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
  2142. * @retval None
  2143. */
  2144. static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
  2145. {
  2146. uint32_t tmp;
  2147. tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
  2148. /* Reset the CCxNE Bit */
  2149. TIMx->CCER &= ~tmp;
  2150. /* Set or reset the CCxNE Bit */
  2151. TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
  2152. }
  2153. /**
  2154. * @}
  2155. */
  2156. #endif /* HAL_TIM_MODULE_ENABLED */
  2157. /**
  2158. * @}
  2159. */
  2160. /**
  2161. * @}
  2162. */