EFTZ_PMU_Bootloader/build/system_stm32f4xx.lst

ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 1


   1              		.cpu cortex-m4
   2              		.arch armv7e-m
   3              		.fpu fpv4-sp-d16
   4              		.eabi_attribute 27, 1
   5              		.eabi_attribute 28, 1
   6              		.eabi_attribute 20, 1
   7              		.eabi_attribute 21, 1
   8              		.eabi_attribute 23, 3
   9              		.eabi_attribute 24, 1
  10              		.eabi_attribute 25, 1
  11              		.eabi_attribute 26, 1
  12              		.eabi_attribute 30, 6
  13              		.eabi_attribute 34, 1
  14              		.eabi_attribute 18, 4
  15              		.file	"system_stm32f4xx.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.global	SystemCoreClock
  20              		.section	.data.SystemCoreClock,"aw"
  21              		.align	2
  24              	SystemCoreClock:
  25 0000 0024F400 		.word	16000000
  26              		.global	AHBPrescTable
  27              		.section	.rodata.AHBPrescTable,"a"
  28              		.align	2
  31              	AHBPrescTable:
  32 0000 00000000 		.ascii	"\000\000\000\000\000\000\000\000\001\002\003\004\006"
  32      00000000 
  32      01020304 
  32      06
  33 000d 070809   		.ascii	"\007\010\011"
  34              		.global	APBPrescTable
  35              		.section	.rodata.APBPrescTable,"a"
  36              		.align	2
  39              	APBPrescTable:
  40 0000 00000000 		.ascii	"\000\000\000\000\001\002\003\004"
  40      01020304 
  41              		.section	.text.SystemInit,"ax",%progbits
  42              		.align	1
  43              		.global	SystemInit
  44              		.syntax unified
  45              		.thumb
  46              		.thumb_func
  48              	SystemInit:
  49              	.LFB235:
  50              		.file 1 "Core/Src/system_stm32f4xx.c"
   1:Core/Src/system_stm32f4xx.c **** /**
   2:Core/Src/system_stm32f4xx.c ****   ******************************************************************************
   3:Core/Src/system_stm32f4xx.c ****   * @file    system_stm32f4xx.c
   4:Core/Src/system_stm32f4xx.c ****   * @author  MCD Application Team
   5:Core/Src/system_stm32f4xx.c ****   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   6:Core/Src/system_stm32f4xx.c ****   *
   7:Core/Src/system_stm32f4xx.c ****   *   This file provides two functions and one global variable to be called from 
   8:Core/Src/system_stm32f4xx.c ****   *   user application:
   9:Core/Src/system_stm32f4xx.c ****   *      - SystemInit(): This function is called at startup just after reset and 
  10:Core/Src/system_stm32f4xx.c ****   *                      before branch to main program. This call is made inside
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 2


  11:Core/Src/system_stm32f4xx.c ****   *                      the "startup_stm32f4xx.s" file.
  12:Core/Src/system_stm32f4xx.c ****   *
  13:Core/Src/system_stm32f4xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  14:Core/Src/system_stm32f4xx.c ****   *                                  by the user application to setup the SysTick 
  15:Core/Src/system_stm32f4xx.c ****   *                                  timer or configure other parameters.
  16:Core/Src/system_stm32f4xx.c ****   *                                     
  17:Core/Src/system_stm32f4xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18:Core/Src/system_stm32f4xx.c ****   *                                 be called whenever the core clock is changed
  19:Core/Src/system_stm32f4xx.c ****   *                                 during program execution.
  20:Core/Src/system_stm32f4xx.c ****   *
  21:Core/Src/system_stm32f4xx.c ****   *
  22:Core/Src/system_stm32f4xx.c ****   ******************************************************************************
  23:Core/Src/system_stm32f4xx.c ****   * @attention
  24:Core/Src/system_stm32f4xx.c ****   *
  25:Core/Src/system_stm32f4xx.c ****   * Copyright (c) 2017 STMicroelectronics.
  26:Core/Src/system_stm32f4xx.c ****   * All rights reserved.
  27:Core/Src/system_stm32f4xx.c ****   *
  28:Core/Src/system_stm32f4xx.c ****   * This software is licensed under terms that can be found in the LICENSE file
  29:Core/Src/system_stm32f4xx.c ****   * in the root directory of this software component.
  30:Core/Src/system_stm32f4xx.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  31:Core/Src/system_stm32f4xx.c ****   *
  32:Core/Src/system_stm32f4xx.c ****   ******************************************************************************
  33:Core/Src/system_stm32f4xx.c ****   */
  34:Core/Src/system_stm32f4xx.c **** 
  35:Core/Src/system_stm32f4xx.c **** /** @addtogroup CMSIS
  36:Core/Src/system_stm32f4xx.c ****   * @{
  37:Core/Src/system_stm32f4xx.c ****   */
  38:Core/Src/system_stm32f4xx.c **** 
  39:Core/Src/system_stm32f4xx.c **** /** @addtogroup stm32f4xx_system
  40:Core/Src/system_stm32f4xx.c ****   * @{
  41:Core/Src/system_stm32f4xx.c ****   */  
  42:Core/Src/system_stm32f4xx.c ****   
  43:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Includes
  44:Core/Src/system_stm32f4xx.c ****   * @{
  45:Core/Src/system_stm32f4xx.c ****   */
  46:Core/Src/system_stm32f4xx.c **** 
  47:Core/Src/system_stm32f4xx.c **** 
  48:Core/Src/system_stm32f4xx.c **** #include "stm32f4xx.h"
  49:Core/Src/system_stm32f4xx.c **** 
  50:Core/Src/system_stm32f4xx.c **** #if !defined  (HSE_VALUE) 
  51:Core/Src/system_stm32f4xx.c ****   #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
  52:Core/Src/system_stm32f4xx.c **** #endif /* HSE_VALUE */
  53:Core/Src/system_stm32f4xx.c **** 
  54:Core/Src/system_stm32f4xx.c **** #if !defined  (HSI_VALUE)
  55:Core/Src/system_stm32f4xx.c ****   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
  56:Core/Src/system_stm32f4xx.c **** #endif /* HSI_VALUE */
  57:Core/Src/system_stm32f4xx.c **** 
  58:Core/Src/system_stm32f4xx.c **** /**
  59:Core/Src/system_stm32f4xx.c ****   * @}
  60:Core/Src/system_stm32f4xx.c ****   */
  61:Core/Src/system_stm32f4xx.c **** 
  62:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
  63:Core/Src/system_stm32f4xx.c ****   * @{
  64:Core/Src/system_stm32f4xx.c ****   */
  65:Core/Src/system_stm32f4xx.c **** 
  66:Core/Src/system_stm32f4xx.c **** /**
  67:Core/Src/system_stm32f4xx.c ****   * @}
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 3


  68:Core/Src/system_stm32f4xx.c ****   */
  69:Core/Src/system_stm32f4xx.c **** 
  70:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Defines
  71:Core/Src/system_stm32f4xx.c ****   * @{
  72:Core/Src/system_stm32f4xx.c ****   */
  73:Core/Src/system_stm32f4xx.c **** 
  74:Core/Src/system_stm32f4xx.c **** /************************* Miscellaneous Configuration ************************/
  75:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
  76:Core/Src/system_stm32f4xx.c **** #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
  77:Core/Src/system_stm32f4xx.c ****  || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  78:Core/Src/system_stm32f4xx.c ****  || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
  79:Core/Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSRAM */
  80:Core/Src/system_stm32f4xx.c **** #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||
  81:Core/Src/system_stm32f4xx.c ****           STM32F412Zx || STM32F412Vx */
  82:Core/Src/system_stm32f4xx.c ****  
  83:Core/Src/system_stm32f4xx.c **** #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
  84:Core/Src/system_stm32f4xx.c ****  || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
  85:Core/Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSDRAM */
  86:Core/Src/system_stm32f4xx.c **** #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||
  87:Core/Src/system_stm32f4xx.c ****           STM32F479xx */
  88:Core/Src/system_stm32f4xx.c **** 
  89:Core/Src/system_stm32f4xx.c **** /* Note: Following vector table addresses must be defined in line with linker
  90:Core/Src/system_stm32f4xx.c ****          configuration. */
  91:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
  92:Core/Src/system_stm32f4xx.c ****      anywhere in Flash or Sram, else the vector table is kept at the automatic
  93:Core/Src/system_stm32f4xx.c ****      remap of boot address selected */
  94:Core/Src/system_stm32f4xx.c **** /* #define USER_VECT_TAB_ADDRESS */
  95:Core/Src/system_stm32f4xx.c **** 
  96:Core/Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
  97:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
  98:Core/Src/system_stm32f4xx.c ****      in Sram else user remap will be done in Flash. */
  99:Core/Src/system_stm32f4xx.c **** /* #define VECT_TAB_SRAM */
 100:Core/Src/system_stm32f4xx.c **** #if defined(VECT_TAB_SRAM)
 101:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
 102:Core/Src/system_stm32f4xx.c ****                                                      This value must be a multiple of 0x200. */
 103:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
 104:Core/Src/system_stm32f4xx.c ****                                                      This value must be a multiple of 0x200. */
 105:Core/Src/system_stm32f4xx.c **** #else
 106:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
 107:Core/Src/system_stm32f4xx.c ****                                                      This value must be a multiple of 0x200. */
 108:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
 109:Core/Src/system_stm32f4xx.c ****                                                      This value must be a multiple of 0x200. */
 110:Core/Src/system_stm32f4xx.c **** #endif /* VECT_TAB_SRAM */
 111:Core/Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 112:Core/Src/system_stm32f4xx.c **** /******************************************************************************/
 113:Core/Src/system_stm32f4xx.c **** 
 114:Core/Src/system_stm32f4xx.c **** /**
 115:Core/Src/system_stm32f4xx.c ****   * @}
 116:Core/Src/system_stm32f4xx.c ****   */
 117:Core/Src/system_stm32f4xx.c **** 
 118:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Macros
 119:Core/Src/system_stm32f4xx.c ****   * @{
 120:Core/Src/system_stm32f4xx.c ****   */
 121:Core/Src/system_stm32f4xx.c **** 
 122:Core/Src/system_stm32f4xx.c **** /**
 123:Core/Src/system_stm32f4xx.c ****   * @}
 124:Core/Src/system_stm32f4xx.c ****   */
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 4


 125:Core/Src/system_stm32f4xx.c **** 
 126:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Variables
 127:Core/Src/system_stm32f4xx.c ****   * @{
 128:Core/Src/system_stm32f4xx.c ****   */
 129:Core/Src/system_stm32f4xx.c ****   /* This variable is updated in three ways:
 130:Core/Src/system_stm32f4xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
 131:Core/Src/system_stm32f4xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 132:Core/Src/system_stm32f4xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
 133:Core/Src/system_stm32f4xx.c ****          Note: If you use this function to configure the system clock; then there
 134:Core/Src/system_stm32f4xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
 135:Core/Src/system_stm32f4xx.c ****                variable is updated automatically.
 136:Core/Src/system_stm32f4xx.c ****   */
 137:Core/Src/system_stm32f4xx.c **** uint32_t SystemCoreClock = 16000000;
 138:Core/Src/system_stm32f4xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 139:Core/Src/system_stm32f4xx.c **** const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 140:Core/Src/system_stm32f4xx.c **** /**
 141:Core/Src/system_stm32f4xx.c ****   * @}
 142:Core/Src/system_stm32f4xx.c ****   */
 143:Core/Src/system_stm32f4xx.c **** 
 144:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
 145:Core/Src/system_stm32f4xx.c ****   * @{
 146:Core/Src/system_stm32f4xx.c ****   */
 147:Core/Src/system_stm32f4xx.c **** 
 148:Core/Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
 149:Core/Src/system_stm32f4xx.c ****   static void SystemInit_ExtMemCtl(void); 
 150:Core/Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 151:Core/Src/system_stm32f4xx.c **** 
 152:Core/Src/system_stm32f4xx.c **** /**
 153:Core/Src/system_stm32f4xx.c ****   * @}
 154:Core/Src/system_stm32f4xx.c ****   */
 155:Core/Src/system_stm32f4xx.c **** 
 156:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Functions
 157:Core/Src/system_stm32f4xx.c ****   * @{
 158:Core/Src/system_stm32f4xx.c ****   */
 159:Core/Src/system_stm32f4xx.c **** 
 160:Core/Src/system_stm32f4xx.c **** /**
 161:Core/Src/system_stm32f4xx.c ****   * @brief  Setup the microcontroller system
 162:Core/Src/system_stm32f4xx.c ****   *         Initialize the FPU setting, vector table location and External memory 
 163:Core/Src/system_stm32f4xx.c ****   *         configuration.
 164:Core/Src/system_stm32f4xx.c ****   * @param  None
 165:Core/Src/system_stm32f4xx.c ****   * @retval None
 166:Core/Src/system_stm32f4xx.c ****   */
 167:Core/Src/system_stm32f4xx.c **** void SystemInit(void)
 168:Core/Src/system_stm32f4xx.c **** {
  51              		.loc 1 168 1
  52              		.cfi_startproc
  53              		@ args = 0, pretend = 0, frame = 0
  54              		@ frame_needed = 1, uses_anonymous_args = 0
  55              		@ link register save eliminated.
  56 0000 80B4     		push	{r7}
  57              	.LCFI0:
  58              		.cfi_def_cfa_offset 4
  59              		.cfi_offset 7, -4
  60 0002 00AF     		add	r7, sp, #0
  61              	.LCFI1:
  62              		.cfi_def_cfa_register 7
 169:Core/Src/system_stm32f4xx.c ****   /* FPU settings ------------------------------------------------------------*/
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 5


 170:Core/Src/system_stm32f4xx.c ****   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 171:Core/Src/system_stm32f4xx.c ****     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
  63              		.loc 1 171 16
  64 0004 064B     		ldr	r3, .L2
  65 0006 D3F88830 		ldr	r3, [r3, #136]
  66 000a 054A     		ldr	r2, .L2
  67 000c 43F47003 		orr	r3, r3, #15728640
  68 0010 C2F88830 		str	r3, [r2, #136]
 172:Core/Src/system_stm32f4xx.c ****   #endif
 173:Core/Src/system_stm32f4xx.c **** 
 174:Core/Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
 175:Core/Src/system_stm32f4xx.c ****   SystemInit_ExtMemCtl(); 
 176:Core/Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 177:Core/Src/system_stm32f4xx.c **** 
 178:Core/Src/system_stm32f4xx.c ****   /* Configure the Vector Table location -------------------------------------*/
 179:Core/Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 180:Core/Src/system_stm32f4xx.c ****   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM 
 181:Core/Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 182:Core/Src/system_stm32f4xx.c **** }
  69              		.loc 1 182 1
  70 0014 00BF     		nop
  71 0016 BD46     		mov	sp, r7
  72              	.LCFI2:
  73              		.cfi_def_cfa_register 13
  74              		@ sp needed
  75 0018 5DF8047B 		ldr	r7, [sp], #4
  76              	.LCFI3:
  77              		.cfi_restore 7
  78              		.cfi_def_cfa_offset 0
  79 001c 7047     		bx	lr
  80              	.L3:
  81 001e 00BF     		.align	2
  82              	.L2:
  83 0020 00ED00E0 		.word	-536810240
  84              		.cfi_endproc
  85              	.LFE235:
  87              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
  88              		.align	1
  89              		.global	SystemCoreClockUpdate
  90              		.syntax unified
  91              		.thumb
  92              		.thumb_func
  94              	SystemCoreClockUpdate:
  95              	.LFB236:
 183:Core/Src/system_stm32f4xx.c **** 
 184:Core/Src/system_stm32f4xx.c **** /**
 185:Core/Src/system_stm32f4xx.c ****    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 186:Core/Src/system_stm32f4xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 187:Core/Src/system_stm32f4xx.c ****   *         be used by the user application to setup the SysTick timer or configure
 188:Core/Src/system_stm32f4xx.c ****   *         other parameters.
 189:Core/Src/system_stm32f4xx.c ****   *           
 190:Core/Src/system_stm32f4xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
 191:Core/Src/system_stm32f4xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 192:Core/Src/system_stm32f4xx.c ****   *         based on this variable will be incorrect.         
 193:Core/Src/system_stm32f4xx.c ****   *     
 194:Core/Src/system_stm32f4xx.c ****   * @note   - The system frequency computed by this function is not the real 
 195:Core/Src/system_stm32f4xx.c ****   *           frequency in the chip. It is calculated based on the predefined 
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 6


 196:Core/Src/system_stm32f4xx.c ****   *           constant and the selected clock source:
 197:Core/Src/system_stm32f4xx.c ****   *             
 198:Core/Src/system_stm32f4xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 199:Core/Src/system_stm32f4xx.c ****   *                                              
 200:Core/Src/system_stm32f4xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 201:Core/Src/system_stm32f4xx.c ****   *                          
 202:Core/Src/system_stm32f4xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
 203:Core/Src/system_stm32f4xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 204:Core/Src/system_stm32f4xx.c ****   *         
 205:Core/Src/system_stm32f4xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
 206:Core/Src/system_stm32f4xx.c ****   *             16 MHz) but the real value may vary depending on the variations
 207:Core/Src/system_stm32f4xx.c ****   *             in voltage and temperature.   
 208:Core/Src/system_stm32f4xx.c ****   *    
 209:Core/Src/system_stm32f4xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
 210:Core/Src/system_stm32f4xx.c ****   *              depends on the application requirements), user has to ensure that HSE_VALUE
 211:Core/Src/system_stm32f4xx.c ****   *              is same as the real frequency of the crystal used. Otherwise, this function
 212:Core/Src/system_stm32f4xx.c ****   *              may have wrong result.
 213:Core/Src/system_stm32f4xx.c ****   *                
 214:Core/Src/system_stm32f4xx.c ****   *         - The result of this function could be not correct when using fractional
 215:Core/Src/system_stm32f4xx.c ****   *           value for HSE crystal.
 216:Core/Src/system_stm32f4xx.c ****   *     
 217:Core/Src/system_stm32f4xx.c ****   * @param  None
 218:Core/Src/system_stm32f4xx.c ****   * @retval None
 219:Core/Src/system_stm32f4xx.c ****   */
 220:Core/Src/system_stm32f4xx.c **** void SystemCoreClockUpdate(void)
 221:Core/Src/system_stm32f4xx.c **** {
  96              		.loc 1 221 1
  97              		.cfi_startproc
  98              		@ args = 0, pretend = 0, frame = 24
  99              		@ frame_needed = 1, uses_anonymous_args = 0
 100              		@ link register save eliminated.
 101 0000 80B4     		push	{r7}
 102              	.LCFI4:
 103              		.cfi_def_cfa_offset 4
 104              		.cfi_offset 7, -4
 105 0002 87B0     		sub	sp, sp, #28
 106              	.LCFI5:
 107              		.cfi_def_cfa_offset 32
 108 0004 00AF     		add	r7, sp, #0
 109              	.LCFI6:
 110              		.cfi_def_cfa_register 7
 222:Core/Src/system_stm32f4xx.c ****   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 111              		.loc 1 222 12
 112 0006 0023     		movs	r3, #0
 113 0008 3B61     		str	r3, [r7, #16]
 114              		.loc 1 222 21
 115 000a 0023     		movs	r3, #0
 116 000c 7B61     		str	r3, [r7, #20]
 117              		.loc 1 222 33
 118 000e 0223     		movs	r3, #2
 119 0010 FB60     		str	r3, [r7, #12]
 120              		.loc 1 222 43
 121 0012 0023     		movs	r3, #0
 122 0014 BB60     		str	r3, [r7, #8]
 123              		.loc 1 222 58
 124 0016 0223     		movs	r3, #2
 125 0018 7B60     		str	r3, [r7, #4]
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 7


 223:Core/Src/system_stm32f4xx.c ****   
 224:Core/Src/system_stm32f4xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 225:Core/Src/system_stm32f4xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
 126              		.loc 1 225 12
 127 001a 344B     		ldr	r3, .L12
 128 001c 9B68     		ldr	r3, [r3, #8]
 129              		.loc 1 225 7
 130 001e 03F00C03 		and	r3, r3, #12
 131 0022 3B61     		str	r3, [r7, #16]
 226:Core/Src/system_stm32f4xx.c **** 
 227:Core/Src/system_stm32f4xx.c ****   switch (tmp)
 132              		.loc 1 227 3
 133 0024 3B69     		ldr	r3, [r7, #16]
 134 0026 082B     		cmp	r3, #8
 135 0028 11D0     		beq	.L5
 136 002a 3B69     		ldr	r3, [r7, #16]
 137 002c 082B     		cmp	r3, #8
 138 002e 44D8     		bhi	.L6
 139 0030 3B69     		ldr	r3, [r7, #16]
 140 0032 002B     		cmp	r3, #0
 141 0034 03D0     		beq	.L7
 142 0036 3B69     		ldr	r3, [r7, #16]
 143 0038 042B     		cmp	r3, #4
 144 003a 04D0     		beq	.L8
 145 003c 3DE0     		b	.L6
 146              	.L7:
 228:Core/Src/system_stm32f4xx.c ****   {
 229:Core/Src/system_stm32f4xx.c ****     case 0x00:  /* HSI used as system clock source */
 230:Core/Src/system_stm32f4xx.c ****       SystemCoreClock = HSI_VALUE;
 147              		.loc 1 230 23
 148 003e 2C4B     		ldr	r3, .L12+4
 149 0040 2C4A     		ldr	r2, .L12+8
 150 0042 1A60     		str	r2, [r3]
 231:Core/Src/system_stm32f4xx.c ****       break;
 151              		.loc 1 231 7
 152 0044 3DE0     		b	.L9
 153              	.L8:
 232:Core/Src/system_stm32f4xx.c ****     case 0x04:  /* HSE used as system clock source */
 233:Core/Src/system_stm32f4xx.c ****       SystemCoreClock = HSE_VALUE;
 154              		.loc 1 233 23
 155 0046 2A4B     		ldr	r3, .L12+4
 156 0048 2B4A     		ldr	r2, .L12+12
 157 004a 1A60     		str	r2, [r3]
 234:Core/Src/system_stm32f4xx.c ****       break;
 158              		.loc 1 234 7
 159 004c 39E0     		b	.L9
 160              	.L5:
 235:Core/Src/system_stm32f4xx.c ****     case 0x08:  /* PLL used as system clock source */
 236:Core/Src/system_stm32f4xx.c **** 
 237:Core/Src/system_stm32f4xx.c ****       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 238:Core/Src/system_stm32f4xx.c ****          SYSCLK = PLL_VCO / PLL_P
 239:Core/Src/system_stm32f4xx.c ****          */    
 240:Core/Src/system_stm32f4xx.c ****       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 161              		.loc 1 240 23
 162 004e 274B     		ldr	r3, .L12
 163 0050 5B68     		ldr	r3, [r3, #4]
 164              		.loc 1 240 55
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 8


 165 0052 9B0D     		lsrs	r3, r3, #22
 166              		.loc 1 240 17
 167 0054 03F00103 		and	r3, r3, #1
 168 0058 BB60     		str	r3, [r7, #8]
 241:Core/Src/system_stm32f4xx.c ****       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 169              		.loc 1 241 17
 170 005a 244B     		ldr	r3, .L12
 171 005c 5B68     		ldr	r3, [r3, #4]
 172              		.loc 1 241 12
 173 005e 03F03F03 		and	r3, r3, #63
 174 0062 7B60     		str	r3, [r7, #4]
 242:Core/Src/system_stm32f4xx.c ****       
 243:Core/Src/system_stm32f4xx.c ****       if (pllsource != 0)
 175              		.loc 1 243 10
 176 0064 BB68     		ldr	r3, [r7, #8]
 177 0066 002B     		cmp	r3, #0
 178 0068 0CD0     		beq	.L10
 244:Core/Src/system_stm32f4xx.c ****       {
 245:Core/Src/system_stm32f4xx.c ****         /* HSE used as PLL clock source */
 246:Core/Src/system_stm32f4xx.c ****         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 179              		.loc 1 246 29
 180 006a 234A     		ldr	r2, .L12+12
 181 006c 7B68     		ldr	r3, [r7, #4]
 182 006e B2FBF3F3 		udiv	r3, r2, r3
 183              		.loc 1 246 44
 184 0072 1E4A     		ldr	r2, .L12
 185 0074 5268     		ldr	r2, [r2, #4]
 186              		.loc 1 246 74
 187 0076 9209     		lsrs	r2, r2, #6
 188 0078 C2F30802 		ubfx	r2, r2, #0, #9
 189              		.loc 1 246 16
 190 007c 02FB03F3 		mul	r3, r2, r3
 191 0080 7B61     		str	r3, [r7, #20]
 192 0082 0BE0     		b	.L11
 193              	.L10:
 247:Core/Src/system_stm32f4xx.c ****       }
 248:Core/Src/system_stm32f4xx.c ****       else
 249:Core/Src/system_stm32f4xx.c ****       {
 250:Core/Src/system_stm32f4xx.c ****         /* HSI used as PLL clock source */
 251:Core/Src/system_stm32f4xx.c ****         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 194              		.loc 1 251 29
 195 0084 1B4A     		ldr	r2, .L12+8
 196 0086 7B68     		ldr	r3, [r7, #4]
 197 0088 B2FBF3F3 		udiv	r3, r2, r3
 198              		.loc 1 251 44
 199 008c 174A     		ldr	r2, .L12
 200 008e 5268     		ldr	r2, [r2, #4]
 201              		.loc 1 251 74
 202 0090 9209     		lsrs	r2, r2, #6
 203 0092 C2F30802 		ubfx	r2, r2, #0, #9
 204              		.loc 1 251 16
 205 0096 02FB03F3 		mul	r3, r2, r3
 206 009a 7B61     		str	r3, [r7, #20]
 207              	.L11:
 252:Core/Src/system_stm32f4xx.c ****       }
 253:Core/Src/system_stm32f4xx.c **** 
 254:Core/Src/system_stm32f4xx.c ****       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 9


 208              		.loc 1 254 20
 209 009c 134B     		ldr	r3, .L12
 210 009e 5B68     		ldr	r3, [r3, #4]
 211              		.loc 1 254 50
 212 00a0 1B0C     		lsrs	r3, r3, #16
 213 00a2 03F00303 		and	r3, r3, #3
 214              		.loc 1 254 56
 215 00a6 0133     		adds	r3, r3, #1
 216              		.loc 1 254 12
 217 00a8 5B00     		lsls	r3, r3, #1
 218 00aa FB60     		str	r3, [r7, #12]
 255:Core/Src/system_stm32f4xx.c ****       SystemCoreClock = pllvco/pllp;
 219              		.loc 1 255 31
 220 00ac 7A69     		ldr	r2, [r7, #20]
 221 00ae FB68     		ldr	r3, [r7, #12]
 222 00b0 B2FBF3F3 		udiv	r3, r2, r3
 223              		.loc 1 255 23
 224 00b4 0E4A     		ldr	r2, .L12+4
 225 00b6 1360     		str	r3, [r2]
 256:Core/Src/system_stm32f4xx.c ****       break;
 226              		.loc 1 256 7
 227 00b8 03E0     		b	.L9
 228              	.L6:
 257:Core/Src/system_stm32f4xx.c ****     default:
 258:Core/Src/system_stm32f4xx.c ****       SystemCoreClock = HSI_VALUE;
 229              		.loc 1 258 23
 230 00ba 0D4B     		ldr	r3, .L12+4
 231 00bc 0D4A     		ldr	r2, .L12+8
 232 00be 1A60     		str	r2, [r3]
 259:Core/Src/system_stm32f4xx.c ****       break;
 233              		.loc 1 259 7
 234 00c0 00BF     		nop
 235              	.L9:
 260:Core/Src/system_stm32f4xx.c ****   }
 261:Core/Src/system_stm32f4xx.c ****   /* Compute HCLK frequency --------------------------------------------------*/
 262:Core/Src/system_stm32f4xx.c ****   /* Get HCLK prescaler */
 263:Core/Src/system_stm32f4xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 236              		.loc 1 263 28
 237 00c2 0A4B     		ldr	r3, .L12
 238 00c4 9B68     		ldr	r3, [r3, #8]
 239              		.loc 1 263 52
 240 00c6 1B09     		lsrs	r3, r3, #4
 241 00c8 03F00F03 		and	r3, r3, #15
 242              		.loc 1 263 22
 243 00cc 0B4A     		ldr	r2, .L12+16
 244 00ce D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
 245              		.loc 1 263 7
 246 00d0 3B61     		str	r3, [r7, #16]
 264:Core/Src/system_stm32f4xx.c ****   /* HCLK frequency */
 265:Core/Src/system_stm32f4xx.c ****   SystemCoreClock >>= tmp;
 247              		.loc 1 265 19
 248 00d2 074B     		ldr	r3, .L12+4
 249 00d4 1A68     		ldr	r2, [r3]
 250 00d6 3B69     		ldr	r3, [r7, #16]
 251 00d8 22FA03F3 		lsr	r3, r2, r3
 252 00dc 044A     		ldr	r2, .L12+4
 253 00de 1360     		str	r3, [r2]
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 10


 266:Core/Src/system_stm32f4xx.c **** }
 254              		.loc 1 266 1
 255 00e0 00BF     		nop
 256 00e2 1C37     		adds	r7, r7, #28
 257              	.LCFI7:
 258              		.cfi_def_cfa_offset 4
 259 00e4 BD46     		mov	sp, r7
 260              	.LCFI8:
 261              		.cfi_def_cfa_register 13
 262              		@ sp needed
 263 00e6 5DF8047B 		ldr	r7, [sp], #4
 264              	.LCFI9:
 265              		.cfi_restore 7
 266              		.cfi_def_cfa_offset 0
 267 00ea 7047     		bx	lr
 268              	.L13:
 269              		.align	2
 270              	.L12:
 271 00ec 00380240 		.word	1073887232
 272 00f0 00000000 		.word	SystemCoreClock
 273 00f4 0024F400 		.word	16000000
 274 00f8 00127A00 		.word	8000000
 275 00fc 00000000 		.word	AHBPrescTable
 276              		.cfi_endproc
 277              	.LFE236:
 279              		.text
 280              	.Letext0:
 281              		.file 2 "d:\\arm-gcc\\arm-none-eabi\\include\\machine\\_default_types.h"
 282              		.file 3 "d:\\arm-gcc\\arm-none-eabi\\include\\sys\\_stdint.h"
 283              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
 284              		.file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h"
 285              		.file 6 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h"
ARM GAS  C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s 			page 11


DEFINED SYMBOLS
                            *ABS*:00000000 system_stm32f4xx.c
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:24     .data.SystemCoreClock:00000000 SystemCoreClock
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:21     .data.SystemCoreClock:00000000 $d
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:31     .rodata.AHBPrescTable:00000000 AHBPrescTable
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:28     .rodata.AHBPrescTable:00000000 $d
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:39     .rodata.APBPrescTable:00000000 APBPrescTable
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:36     .rodata.APBPrescTable:00000000 $d
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:42     .text.SystemInit:00000000 $t
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:48     .text.SystemInit:00000000 SystemInit
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:83     .text.SystemInit:00000020 $d
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:88     .text.SystemCoreClockUpdate:00000000 $t
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:94     .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
C:\Users\10728\AppData\Local\Temp\ccgjYoCB.s:271    .text.SystemCoreClockUpdate:000000ec $d

NO UNDEFINED SYMBOLS