ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 6 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "stm32f4xx_hal_pwr.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .section .text.HAL_PWR_DeInit,"ax",%progbits 20 .align 1 21 .global HAL_PWR_DeInit 22 .syntax unified 23 .thumb 24 .thumb_func 26 HAL_PWR_DeInit: 27 .LFB235: 28 .file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @file stm32f4xx_hal_pwr.c 4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @author MCD Application Team 5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR HAL module driver. 6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: 8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * + Initialization and de-initialization functions 9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * + Peripheral Control functions 10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @attention 13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Copyright (c) 2017 STMicroelectronics. 15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * All rights reserved. 16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file in 18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * the root directory of this software component. 19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ 24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #include "stm32f4xx_hal.h" 25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @addtogroup STM32F4xx_HAL_Driver 27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR PWR ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 2 31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR HAL module driver 32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED 36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ 38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ 39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @addtogroup PWR_Private_Constants 40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask 44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_MODE_IT 0x00010000U 47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_MODE_EVT 0x00020000U 48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_RISING_EDGE 0x00000001U 49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_FALLING_EDGE 0x00000002U 50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ 58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ 59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ 60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ 61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions 63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Initialization and de-initialization functions 68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @verbatim 70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### 72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data 75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted 76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** write accesses. 77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: 78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the 79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. 80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. 81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @endverbatim 83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 3 88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DeInit(void) 91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 29 .loc 1 91 1 30 .cfi_startproc 31 @ args = 0, pretend = 0, frame = 0 32 @ frame_needed = 1, uses_anonymous_args = 0 33 @ link register save eliminated. 34 0000 80B4 push {r7} 35 .LCFI0: 36 .cfi_def_cfa_offset 4 37 .cfi_offset 7, -4 38 0002 00AF add r7, sp, #0 39 .LCFI1: 40 .cfi_def_cfa_register 7 92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); 41 .loc 1 92 3 42 0004 084B ldr r3, .L2 43 0006 1B6A ldr r3, [r3, #32] 44 0008 074A ldr r2, .L2 45 000a 43F08053 orr r3, r3, #268435456 46 000e 1362 str r3, [r2, #32] 93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); 47 .loc 1 93 3 48 0010 054B ldr r3, .L2 49 0012 1B6A ldr r3, [r3, #32] 50 0014 044A ldr r2, .L2 51 0016 23F08053 bic r3, r3, #268435456 52 001a 1362 str r3, [r2, #32] 94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 53 .loc 1 94 1 54 001c 00BF nop 55 001e BD46 mov sp, r7 56 .LCFI2: 57 .cfi_def_cfa_register 13 58 @ sp needed 59 0020 5DF8047B ldr r7, [sp], #4 60 .LCFI3: 61 .cfi_restore 7 62 .cfi_def_cfa_offset 0 63 0024 7047 bx lr 64 .L3: 65 0026 00BF .align 2 66 .L2: 67 0028 00380240 .word 1073887232 68 .cfi_endproc 69 .LFE235: 71 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits 72 .align 1 73 .global HAL_PWR_EnableBkUpAccess 74 .syntax unified 75 .thumb 76 .thumb_func 78 HAL_PWR_EnableBkUpAccess: 79 .LFB236: 95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 4 96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC 98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * backup data registers and backup SRAM). 99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. 101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note The following sequence is required to bypass the delay between 102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * DBP bit programming and the effective enabling of the backup domain. 103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Please check the Errata Sheet for more details under "Possible delay 104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * in backup domain protection disabling/enabling after programming the 105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * DBP bit" section. 106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) 109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 80 .loc 1 109 1 81 .cfi_startproc 82 @ args = 0, pretend = 0, frame = 8 83 @ frame_needed = 1, uses_anonymous_args = 0 84 @ link register save eliminated. 85 0000 80B4 push {r7} 86 .LCFI4: 87 .cfi_def_cfa_offset 4 88 .cfi_offset 7, -4 89 0002 83B0 sub sp, sp, #12 90 .LCFI5: 91 .cfi_def_cfa_offset 16 92 0004 00AF add r7, sp, #0 93 .LCFI6: 94 .cfi_def_cfa_register 7 110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __IO uint32_t dummyread; 111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 95 .loc 1 111 3 96 0006 064B ldr r3, .L5 97 .loc 1 111 32 98 0008 0122 movs r2, #1 99 000a 1A60 str r2, [r3] 112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** dummyread = PWR->CR; 100 .loc 1 112 18 101 000c 054B ldr r3, .L5+4 102 000e 1B68 ldr r3, [r3] 103 .loc 1 112 13 104 0010 7B60 str r3, [r7, #4] 113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** UNUSED(dummyread); 105 .loc 1 113 3 106 0012 7B68 ldr r3, [r7, #4] 114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 107 .loc 1 114 1 108 0014 00BF nop 109 0016 0C37 adds r7, r7, #12 110 .LCFI7: 111 .cfi_def_cfa_offset 4 112 0018 BD46 mov sp, r7 113 .LCFI8: 114 .cfi_def_cfa_register 13 115 @ sp needed 116 001a 5DF8047B ldr r7, [sp], #4 117 .LCFI9: ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 5 118 .cfi_restore 7 119 .cfi_def_cfa_offset 0 120 001e 7047 bx lr 121 .L6: 122 .align 2 123 .L5: 124 0020 20000E42 .word 1108213792 125 0024 00700040 .word 1073770496 126 .cfi_endproc 127 .LFE236: 129 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits 130 .align 1 131 .global HAL_PWR_DisableBkUpAccess 132 .syntax unified 133 .thumb 134 .thumb_func 136 HAL_PWR_DisableBkUpAccess: 137 .LFB237: 115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC 118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * backup data registers and backup SRAM). 119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. 121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note The following sequence is required to bypass the delay between 122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * DBP bit programming and the effective disabling of the backup domain. 123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Please check the Errata Sheet for more details under "Possible delay 124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * in backup domain protection disabling/enabling after programming the 125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * DBP bit" section. 126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) 129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 138 .loc 1 129 1 139 .cfi_startproc 140 @ args = 0, pretend = 0, frame = 8 141 @ frame_needed = 1, uses_anonymous_args = 0 142 @ link register save eliminated. 143 0000 80B4 push {r7} 144 .LCFI10: 145 .cfi_def_cfa_offset 4 146 .cfi_offset 7, -4 147 0002 83B0 sub sp, sp, #12 148 .LCFI11: 149 .cfi_def_cfa_offset 16 150 0004 00AF add r7, sp, #0 151 .LCFI12: 152 .cfi_def_cfa_register 7 130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __IO uint32_t dummyread; 131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; 153 .loc 1 131 3 154 0006 064B ldr r3, .L8 155 .loc 1 131 32 156 0008 0022 movs r2, #0 157 000a 1A60 str r2, [r3] 132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** dummyread = PWR->CR; 158 .loc 1 132 18 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 6 159 000c 054B ldr r3, .L8+4 160 000e 1B68 ldr r3, [r3] 161 .loc 1 132 13 162 0010 7B60 str r3, [r7, #4] 133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** UNUSED(dummyread); 163 .loc 1 133 3 164 0012 7B68 ldr r3, [r7, #4] 134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 165 .loc 1 134 1 166 0014 00BF nop 167 0016 0C37 adds r7, r7, #12 168 .LCFI13: 169 .cfi_def_cfa_offset 4 170 0018 BD46 mov sp, r7 171 .LCFI14: 172 .cfi_def_cfa_register 13 173 @ sp needed 174 001a 5DF8047B ldr r7, [sp], #4 175 .LCFI15: 176 .cfi_restore 7 177 .cfi_def_cfa_offset 0 178 001e 7047 bx lr 179 .L9: 180 .align 2 181 .L8: 182 0020 20000E42 .word 1108213792 183 0024 00700040 .word 1073770496 184 .cfi_endproc 185 .LFE237: 187 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits 188 .align 1 189 .global HAL_PWR_ConfigPVD 190 .syntax unified 191 .thumb 192 .thumb_func 194 HAL_PWR_ConfigPVD: 195 .LFB238: 135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Low Power modes configuration functions 142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @verbatim 144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ##### Peripheral Control functions ##### 147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** PVD configuration *** 150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ========================= 151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a 153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 7 155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI 156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through 157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. 158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode. 159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Wake-up pin configuration *** 161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================================ 162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges. 165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. 166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: 168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Low Power modes configuration *** 170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ===================================== 171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The devices feature 3 low-power modes: 173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. 174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator 175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** in low power mode 176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off. 177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Sleep mode *** 179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================== 180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Entry: 182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLE 183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** functions with 184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** -@@- The Regulator parameter is not used for the STM32F4 family 188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** and is kept as parameter just to maintain compatibility with the 189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** lower power families (STM32L). 190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Exit: 191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Any peripheral interrupt acknowledged by the nested vectored interrupt 192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. 193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Stop mode *** 195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================= 196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, 198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents 199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** are preserved. 200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode. 201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** To minimize the consumption In Stop mode, FLASH can be powered off before 202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. 203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** It can be switched on again by software after exiting the Stop mode using 204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HAL_PWREx_DisableFlashPowerDown() function. 205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Entry: 207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** function with: 209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Main regulator ON. 210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Low Power regulator ON. 211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Exit: ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 8 212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Any EXTI Line (Internal or External) configured in Interrupt/Event mode. 213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Standby mode *** 215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ==================== 216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) 218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based 219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost 222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby 223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** circuitry. 224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The voltage regulator is OFF. 226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Entry: 228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. 229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Exit: 230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, 231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset. 232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Auto-wake-up (AWU) from low-power mode *** 234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ============================================= 235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Wake-up event, a tamper event or a time-stamp event, without depending on 239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** an external interrupt (Auto-wake-up mode). 240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) RTC auto-wake-up (AWU) from the Stop and Standby modes 242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. 245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 246:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 247:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the 248:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. 249:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 250:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to 251:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTime 252:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 253:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @endverbatim 254:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 255:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 256:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 257:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 258:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 259:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration 260:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * information for the PVD. 261:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for 262:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each 263:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * detection level. 264:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 265:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 266:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 267:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 196 .loc 1 267 1 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 9 197 .cfi_startproc 198 @ args = 0, pretend = 0, frame = 8 199 @ frame_needed = 1, uses_anonymous_args = 0 200 @ link register save eliminated. 201 0000 80B4 push {r7} 202 .LCFI16: 203 .cfi_def_cfa_offset 4 204 .cfi_offset 7, -4 205 0002 83B0 sub sp, sp, #12 206 .LCFI17: 207 .cfi_def_cfa_offset 16 208 0004 00AF add r7, sp, #0 209 .LCFI18: 210 .cfi_def_cfa_register 7 211 0006 7860 str r0, [r7, #4] 268:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 269:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 270:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 271:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 272:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */ 273:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 212 .loc 1 273 3 213 0008 2B4B ldr r3, .L16 214 000a 1B68 ldr r3, [r3] 215 000c 23F0E002 bic r2, r3, #224 216 0010 7B68 ldr r3, [r7, #4] 217 0012 1B68 ldr r3, [r3] 218 0014 2849 ldr r1, .L16 219 0016 1343 orrs r3, r3, r2 220 0018 0B60 str r3, [r1] 274:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 275:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 276:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 221 .loc 1 276 3 222 001a 284B ldr r3, .L16+4 223 001c 5B68 ldr r3, [r3, #4] 224 001e 274A ldr r2, .L16+4 225 0020 23F48033 bic r3, r3, #65536 226 0024 5360 str r3, [r2, #4] 277:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); 227 .loc 1 277 3 228 0026 254B ldr r3, .L16+4 229 0028 1B68 ldr r3, [r3] 230 002a 244A ldr r2, .L16+4 231 002c 23F48033 bic r3, r3, #65536 232 0030 1360 str r3, [r2] 278:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); 233 .loc 1 278 3 234 0032 224B ldr r3, .L16+4 235 0034 9B68 ldr r3, [r3, #8] 236 0036 214A ldr r2, .L16+4 237 0038 23F48033 bic r3, r3, #65536 238 003c 9360 str r3, [r2, #8] 279:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 239 .loc 1 279 3 240 003e 1F4B ldr r3, .L16+4 241 0040 DB68 ldr r3, [r3, #12] ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 10 242 0042 1E4A ldr r2, .L16+4 243 0044 23F48033 bic r3, r3, #65536 244 0048 D360 str r3, [r2, #12] 280:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 281:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure interrupt mode */ 282:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 245 .loc 1 282 17 246 004a 7B68 ldr r3, [r7, #4] 247 004c 5B68 ldr r3, [r3, #4] 248 .loc 1 282 24 249 004e 03F48033 and r3, r3, #65536 250 .loc 1 282 5 251 0052 002B cmp r3, #0 252 0054 05D0 beq .L11 283:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 284:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); 253 .loc 1 284 5 254 0056 194B ldr r3, .L16+4 255 0058 1B68 ldr r3, [r3] 256 005a 184A ldr r2, .L16+4 257 005c 43F48033 orr r3, r3, #65536 258 0060 1360 str r3, [r2] 259 .L11: 285:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 286:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 287:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure event mode */ 288:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 260 .loc 1 288 17 261 0062 7B68 ldr r3, [r7, #4] 262 0064 5B68 ldr r3, [r3, #4] 263 .loc 1 288 24 264 0066 03F40033 and r3, r3, #131072 265 .loc 1 288 5 266 006a 002B cmp r3, #0 267 006c 05D0 beq .L12 289:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 290:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 268 .loc 1 290 5 269 006e 134B ldr r3, .L16+4 270 0070 5B68 ldr r3, [r3, #4] 271 0072 124A ldr r2, .L16+4 272 0074 43F48033 orr r3, r3, #65536 273 0078 5360 str r3, [r2, #4] 274 .L12: 291:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 292:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 293:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure the edge */ 294:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 275 .loc 1 294 17 276 007a 7B68 ldr r3, [r7, #4] 277 007c 5B68 ldr r3, [r3, #4] 278 .loc 1 294 24 279 007e 03F00103 and r3, r3, #1 280 .loc 1 294 5 281 0082 002B cmp r3, #0 282 0084 05D0 beq .L13 295:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 11 296:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 283 .loc 1 296 5 284 0086 0D4B ldr r3, .L16+4 285 0088 9B68 ldr r3, [r3, #8] 286 008a 0C4A ldr r2, .L16+4 287 008c 43F48033 orr r3, r3, #65536 288 0090 9360 str r3, [r2, #8] 289 .L13: 297:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 298:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 299:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 290 .loc 1 299 17 291 0092 7B68 ldr r3, [r7, #4] 292 0094 5B68 ldr r3, [r3, #4] 293 .loc 1 299 24 294 0096 03F00203 and r3, r3, #2 295 .loc 1 299 5 296 009a 002B cmp r3, #0 297 009c 05D0 beq .L15 300:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 301:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 298 .loc 1 301 5 299 009e 074B ldr r3, .L16+4 300 00a0 DB68 ldr r3, [r3, #12] 301 00a2 064A ldr r2, .L16+4 302 00a4 43F48033 orr r3, r3, #65536 303 00a8 D360 str r3, [r2, #12] 304 .L15: 302:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 303:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 305 .loc 1 303 1 306 00aa 00BF nop 307 00ac 0C37 adds r7, r7, #12 308 .LCFI19: 309 .cfi_def_cfa_offset 4 310 00ae BD46 mov sp, r7 311 .LCFI20: 312 .cfi_def_cfa_register 13 313 @ sp needed 314 00b0 5DF8047B ldr r7, [sp], #4 315 .LCFI21: 316 .cfi_restore 7 317 .cfi_def_cfa_offset 0 318 00b4 7047 bx lr 319 .L17: 320 00b6 00BF .align 2 321 .L16: 322 00b8 00700040 .word 1073770496 323 00bc 003C0140 .word 1073822720 324 .cfi_endproc 325 .LFE238: 327 .section .text.HAL_PWR_EnablePVD,"ax",%progbits 328 .align 1 329 .global HAL_PWR_EnablePVD 330 .syntax unified 331 .thumb 332 .thumb_func ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 12 334 HAL_PWR_EnablePVD: 335 .LFB239: 304:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 305:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 306:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD). 307:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 308:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 309:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void) 310:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 336 .loc 1 310 1 337 .cfi_startproc 338 @ args = 0, pretend = 0, frame = 0 339 @ frame_needed = 1, uses_anonymous_args = 0 340 @ link register save eliminated. 341 0000 80B4 push {r7} 342 .LCFI22: 343 .cfi_def_cfa_offset 4 344 .cfi_offset 7, -4 345 0002 00AF add r7, sp, #0 346 .LCFI23: 347 .cfi_def_cfa_register 7 311:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; 348 .loc 1 311 3 349 0004 034B ldr r3, .L19 350 .loc 1 311 33 351 0006 0122 movs r2, #1 352 0008 1A60 str r2, [r3] 312:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 353 .loc 1 312 1 354 000a 00BF nop 355 000c BD46 mov sp, r7 356 .LCFI24: 357 .cfi_def_cfa_register 13 358 @ sp needed 359 000e 5DF8047B ldr r7, [sp], #4 360 .LCFI25: 361 .cfi_restore 7 362 .cfi_def_cfa_offset 0 363 0012 7047 bx lr 364 .L20: 365 .align 2 366 .L19: 367 0014 10000E42 .word 1108213776 368 .cfi_endproc 369 .LFE239: 371 .section .text.HAL_PWR_DisablePVD,"ax",%progbits 372 .align 1 373 .global HAL_PWR_DisablePVD 374 .syntax unified 375 .thumb 376 .thumb_func 378 HAL_PWR_DisablePVD: 379 .LFB240: 313:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 314:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 315:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD). 316:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 13 317:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 318:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void) 319:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 380 .loc 1 319 1 381 .cfi_startproc 382 @ args = 0, pretend = 0, frame = 0 383 @ frame_needed = 1, uses_anonymous_args = 0 384 @ link register save eliminated. 385 0000 80B4 push {r7} 386 .LCFI26: 387 .cfi_def_cfa_offset 4 388 .cfi_offset 7, -4 389 0002 00AF add r7, sp, #0 390 .LCFI27: 391 .cfi_def_cfa_register 7 320:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; 392 .loc 1 320 3 393 0004 034B ldr r3, .L22 394 .loc 1 320 33 395 0006 0022 movs r2, #0 396 0008 1A60 str r2, [r3] 321:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 397 .loc 1 321 1 398 000a 00BF nop 399 000c BD46 mov sp, r7 400 .LCFI28: 401 .cfi_def_cfa_register 13 402 @ sp needed 403 000e 5DF8047B ldr r7, [sp], #4 404 .LCFI29: 405 .cfi_restore 7 406 .cfi_def_cfa_offset 0 407 0012 7047 bx lr 408 .L23: 409 .align 2 410 .L22: 411 0014 10000E42 .word 1108213776 412 .cfi_endproc 413 .LFE240: 415 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits 416 .align 1 417 .global HAL_PWR_EnableWakeUpPin 418 .syntax unified 419 .thumb 420 .thumb_func 422 HAL_PWR_EnableWakeUpPin: 423 .LFB241: 322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 323:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 324:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables the Wake-up PINx functionality. 325:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. 326:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 327:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 328:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413x 329:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423x 330:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 331:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 14 332:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) 333:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 424 .loc 1 333 1 425 .cfi_startproc 426 @ args = 0, pretend = 0, frame = 8 427 @ frame_needed = 1, uses_anonymous_args = 0 428 @ link register save eliminated. 429 0000 80B4 push {r7} 430 .LCFI30: 431 .cfi_def_cfa_offset 4 432 .cfi_offset 7, -4 433 0002 83B0 sub sp, sp, #12 434 .LCFI31: 435 .cfi_def_cfa_offset 16 436 0004 00AF add r7, sp, #0 437 .LCFI32: 438 .cfi_def_cfa_register 7 439 0006 7860 str r0, [r7, #4] 334:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameter */ 335:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 336:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 337:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Enable the wake up pin */ 338:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx); 440 .loc 1 338 3 441 0008 054B ldr r3, .L25 442 000a 5A68 ldr r2, [r3, #4] 443 000c 0449 ldr r1, .L25 444 000e 7B68 ldr r3, [r7, #4] 445 0010 1343 orrs r3, r3, r2 446 0012 4B60 str r3, [r1, #4] 339:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 447 .loc 1 339 1 448 0014 00BF nop 449 0016 0C37 adds r7, r7, #12 450 .LCFI33: 451 .cfi_def_cfa_offset 4 452 0018 BD46 mov sp, r7 453 .LCFI34: 454 .cfi_def_cfa_register 13 455 @ sp needed 456 001a 5DF8047B ldr r7, [sp], #4 457 .LCFI35: 458 .cfi_restore 7 459 .cfi_def_cfa_offset 0 460 001e 7047 bx lr 461 .L26: 462 .align 2 463 .L25: 464 0020 00700040 .word 1073770496 465 .cfi_endproc 466 .LFE241: 468 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits 469 .align 1 470 .global HAL_PWR_DisableWakeUpPin 471 .syntax unified 472 .thumb 473 .thumb_func ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 15 475 HAL_PWR_DisableWakeUpPin: 476 .LFB242: 340:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 341:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 342:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables the Wake-up PINx functionality. 343:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. 344:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 345:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 346:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413x 347:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423x 348:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 349:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 350:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) 351:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 477 .loc 1 351 1 478 .cfi_startproc 479 @ args = 0, pretend = 0, frame = 8 480 @ frame_needed = 1, uses_anonymous_args = 0 481 @ link register save eliminated. 482 0000 80B4 push {r7} 483 .LCFI36: 484 .cfi_def_cfa_offset 4 485 .cfi_offset 7, -4 486 0002 83B0 sub sp, sp, #12 487 .LCFI37: 488 .cfi_def_cfa_offset 16 489 0004 00AF add r7, sp, #0 490 .LCFI38: 491 .cfi_def_cfa_register 7 492 0006 7860 str r0, [r7, #4] 352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameter */ 353:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 354:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 355:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Disable the wake up pin */ 356:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx); 493 .loc 1 356 3 494 0008 064B ldr r3, .L28 495 000a 5A68 ldr r2, [r3, #4] 496 000c 7B68 ldr r3, [r7, #4] 497 000e DB43 mvns r3, r3 498 0010 0449 ldr r1, .L28 499 0012 1340 ands r3, r3, r2 500 0014 4B60 str r3, [r1, #4] 357:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 501 .loc 1 357 1 502 0016 00BF nop 503 0018 0C37 adds r7, r7, #12 504 .LCFI39: 505 .cfi_def_cfa_offset 4 506 001a BD46 mov sp, r7 507 .LCFI40: 508 .cfi_def_cfa_register 13 509 @ sp needed 510 001c 5DF8047B ldr r7, [sp], #4 511 .LCFI41: 512 .cfi_restore 7 513 .cfi_def_cfa_offset 0 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 16 514 0020 7047 bx lr 515 .L29: 516 0022 00BF .align 2 517 .L28: 518 0024 00700040 .word 1073770496 519 .cfi_endproc 520 .LFE242: 522 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits 523 .align 1 524 .global HAL_PWR_EnterSLEEPMode 525 .syntax unified 526 .thumb 527 .thumb_func 529 HAL_PWR_EnterSLEEPMode: 530 .LFB243: 358:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 359:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 360:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Sleep mode. 361:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 362:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. 363:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 364:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Sleep mode, the systick is stopped to avoid exit from this mode with 365:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * systick interrupt when used as time base for Timeout 366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 367:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode. 368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 369:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON 370:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON 371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note This parameter is not used for the STM32F4 family and is kept as parameter 372:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * just to maintain compatibility with the lower power families. 373:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. 374:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 375:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 376:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 377:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 379:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) 380:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 531 .loc 1 380 1 532 .cfi_startproc 533 @ args = 0, pretend = 0, frame = 8 534 @ frame_needed = 1, uses_anonymous_args = 0 535 @ link register save eliminated. 536 0000 80B4 push {r7} 537 .LCFI42: 538 .cfi_def_cfa_offset 4 539 .cfi_offset 7, -4 540 0002 83B0 sub sp, sp, #12 541 .LCFI43: 542 .cfi_def_cfa_offset 16 543 0004 00AF add r7, sp, #0 544 .LCFI44: 545 .cfi_def_cfa_register 7 546 0006 7860 str r0, [r7, #4] 547 0008 0B46 mov r3, r1 548 000a FB70 strb r3, [r7, #3] 381:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 17 382:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 383:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); 384:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ 386:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 549 .loc 1 386 3 550 000c 094B ldr r3, .L34 551 000e 1B69 ldr r3, [r3, #16] 552 0010 084A ldr r2, .L34 553 0012 23F00403 bic r3, r3, #4 554 0016 1361 str r3, [r2, #16] 387:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 388:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ 389:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) 555 .loc 1 389 5 556 0018 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 557 001a 012B cmp r3, #1 558 001c 01D1 bne .L31 390:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 391:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 392:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 559 .loc 1 392 5 560 .syntax unified 561 @ 392 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 562 001e 30BF wfi 563 @ 0 "" 2 393:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 394:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** else 395:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 396:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Event */ 397:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __SEV(); 398:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 399:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 400:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 401:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 564 .loc 1 401 1 565 .thumb 566 .syntax unified 567 0020 02E0 b .L33 568 .L31: 397:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 569 .loc 1 397 5 570 .syntax unified 571 @ 397 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 572 0022 40BF sev 573 @ 0 "" 2 398:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 574 .loc 1 398 5 575 @ 398 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 576 0024 20BF wfe 577 @ 0 "" 2 399:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 578 .loc 1 399 5 579 @ 399 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 580 0026 20BF wfe 581 @ 0 "" 2 582 .thumb ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 18 583 .syntax unified 584 .L33: 585 .loc 1 401 1 586 0028 00BF nop 587 002a 0C37 adds r7, r7, #12 588 .LCFI45: 589 .cfi_def_cfa_offset 4 590 002c BD46 mov sp, r7 591 .LCFI46: 592 .cfi_def_cfa_register 13 593 @ sp needed 594 002e 5DF8047B ldr r7, [sp], #4 595 .LCFI47: 596 .cfi_restore 7 597 .cfi_def_cfa_offset 0 598 0032 7047 bx lr 599 .L35: 600 .align 2 601 .L34: 602 0034 00ED00E0 .word -536810240 603 .cfi_endproc 604 .LFE243: 606 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits 607 .align 1 608 .global HAL_PWR_EnterSTOPMode 609 .syntax unified 610 .thumb 611 .thumb_func 613 HAL_PWR_EnterSTOPMode: 614 .LFB244: 402:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 403:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 404:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Stop mode. 405:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. 406:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 407:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock. 408:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional 409:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. 410:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption 411:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * is higher although the startup time is reduced. 412:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in Stop mode. 413:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 414:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON 415:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON 416:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. 417:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 418:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction 419:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction 420:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 421:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 422:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) 423:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 615 .loc 1 423 1 616 .cfi_startproc 617 @ args = 0, pretend = 0, frame = 8 618 @ frame_needed = 1, uses_anonymous_args = 0 619 @ link register save eliminated. ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 19 620 0000 80B4 push {r7} 621 .LCFI48: 622 .cfi_def_cfa_offset 4 623 .cfi_offset 7, -4 624 0002 83B0 sub sp, sp, #12 625 .LCFI49: 626 .cfi_def_cfa_offset 16 627 0004 00AF add r7, sp, #0 628 .LCFI50: 629 .cfi_def_cfa_register 7 630 0006 7860 str r0, [r7, #4] 631 0008 0B46 mov r3, r1 632 000a FB70 strb r3, [r7, #3] 424:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 425:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 426:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 427:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 428:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator val 429:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); 633 .loc 1 429 3 634 000c 104B ldr r3, .L39 635 000e 1B68 ldr r3, [r3] 636 0010 23F00302 bic r2, r3, #3 637 0014 0E49 ldr r1, .L39 638 0016 7B68 ldr r3, [r7, #4] 639 0018 1343 orrs r3, r3, r2 640 001a 0B60 str r3, [r1] 430:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 431:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 432:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 641 .loc 1 432 3 642 001c 0D4B ldr r3, .L39+4 643 001e 1B69 ldr r3, [r3, #16] 644 0020 0C4A ldr r2, .L39+4 645 0022 43F00403 orr r3, r3, #4 646 0026 1361 str r3, [r2, #16] 433:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 434:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/ 435:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) 647 .loc 1 435 5 648 0028 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 649 002a 012B cmp r3, #1 650 002c 01D1 bne .L37 436:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 437:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 438:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 651 .loc 1 438 5 652 .syntax unified 653 @ 438 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 654 002e 30BF wfi 655 @ 0 "" 2 656 .thumb 657 .syntax unified 658 0030 02E0 b .L38 659 .L37: 439:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 440:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** else ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 20 441:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 442:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Event */ 443:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __SEV(); 660 .loc 1 443 5 661 .syntax unified 662 @ 443 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 663 0032 40BF sev 664 @ 0 "" 2 444:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 665 .loc 1 444 5 666 @ 444 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 667 0034 20BF wfe 668 @ 0 "" 2 445:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 669 .loc 1 445 5 670 @ 445 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 671 0036 20BF wfe 672 @ 0 "" 2 673 .thumb 674 .syntax unified 675 .L38: 446:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 447:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ 448:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 676 .loc 1 448 3 677 0038 064B ldr r3, .L39+4 678 003a 1B69 ldr r3, [r3, #16] 679 003c 054A ldr r2, .L39+4 680 003e 23F00403 bic r3, r3, #4 681 0042 1361 str r3, [r2, #16] 449:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 682 .loc 1 449 1 683 0044 00BF nop 684 0046 0C37 adds r7, r7, #12 685 .LCFI51: 686 .cfi_def_cfa_offset 4 687 0048 BD46 mov sp, r7 688 .LCFI52: 689 .cfi_def_cfa_register 13 690 @ sp needed 691 004a 5DF8047B ldr r7, [sp], #4 692 .LCFI53: 693 .cfi_restore 7 694 .cfi_def_cfa_offset 0 695 004e 7047 bx lr 696 .L40: 697 .align 2 698 .L39: 699 0050 00700040 .word 1073770496 700 0054 00ED00E0 .word -536810240 701 .cfi_endproc 702 .LFE244: 704 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits 705 .align 1 706 .global HAL_PWR_EnterSTANDBYMode 707 .syntax unified 708 .thumb ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 21 709 .thumb_func 711 HAL_PWR_EnterSTANDBYMode: 712 .LFB245: 450:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 451:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 452:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Standby mode. 453:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: 454:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - Reset pad (still available) 455:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 456:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out. 457:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. 458:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - WKUP pin 1 (PA0) if enabled. 459:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 460:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 461:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) 462:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 713 .loc 1 462 1 714 .cfi_startproc 715 @ args = 0, pretend = 0, frame = 0 716 @ frame_needed = 1, uses_anonymous_args = 0 717 @ link register save eliminated. 718 0000 80B4 push {r7} 719 .LCFI54: 720 .cfi_def_cfa_offset 4 721 .cfi_offset 7, -4 722 0002 00AF add r7, sp, #0 723 .LCFI55: 724 .cfi_def_cfa_register 7 463:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select Standby mode */ 464:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PDDS); 725 .loc 1 464 3 726 0004 084B ldr r3, .L42 727 0006 1B68 ldr r3, [r3] 728 0008 074A ldr r2, .L42 729 000a 43F00203 orr r3, r3, #2 730 000e 1360 str r3, [r2] 465:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 466:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 467:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 731 .loc 1 467 3 732 0010 064B ldr r3, .L42+4 733 0012 1B69 ldr r3, [r3, #16] 734 0014 054A ldr r2, .L42+4 735 0016 43F00403 orr r3, r3, #4 736 001a 1361 str r3, [r2, #16] 468:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ 470:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #if defined ( __CC_ARM) 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __force_stores(); 472:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #endif 473:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 737 .loc 1 474 3 738 .syntax unified 739 @ 474 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 740 001c 30BF wfi 741 @ 0 "" 2 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 22 475:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 742 .loc 1 475 1 743 .thumb 744 .syntax unified 745 001e 00BF nop 746 0020 BD46 mov sp, r7 747 .LCFI56: 748 .cfi_def_cfa_register 13 749 @ sp needed 750 0022 5DF8047B ldr r7, [sp], #4 751 .LCFI57: 752 .cfi_restore 7 753 .cfi_def_cfa_offset 0 754 0026 7047 bx lr 755 .L43: 756 .align 2 757 .L42: 758 0028 00700040 .word 1073770496 759 002c 00ED00E0 .word -536810240 760 .cfi_endproc 761 .LFE245: 763 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits 764 .align 1 765 .global HAL_PWR_PVD_IRQHandler 766 .syntax unified 767 .thumb 768 .thumb_func 770 HAL_PWR_PVD_IRQHandler: 771 .LFB246: 476:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 477:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 478:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request. 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler(). 480:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 481:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 482:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void) 483:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 772 .loc 1 483 1 773 .cfi_startproc 774 @ args = 0, pretend = 0, frame = 0 775 @ frame_needed = 1, uses_anonymous_args = 0 776 0000 80B5 push {r7, lr} 777 .LCFI58: 778 .cfi_def_cfa_offset 8 779 .cfi_offset 7, -8 780 .cfi_offset 14, -4 781 0002 00AF add r7, sp, #0 782 .LCFI59: 783 .cfi_def_cfa_register 7 484:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check PWR Exti flag */ 485:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 784 .loc 1 485 6 785 0004 064B ldr r3, .L47 786 0006 5B69 ldr r3, [r3, #20] 787 0008 03F48033 and r3, r3, #65536 788 .loc 1 485 5 789 000c 002B cmp r3, #0 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 23 790 000e 05D0 beq .L46 486:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 487:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ 488:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** HAL_PWR_PVDCallback(); 791 .loc 1 488 5 792 0010 FFF7FEFF bl HAL_PWR_PVDCallback 489:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 490:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear PWR Exti pending bit */ 491:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 793 .loc 1 491 5 794 0014 024B ldr r3, .L47 795 0016 4FF48032 mov r2, #65536 796 001a 5A61 str r2, [r3, #20] 797 .L46: 492:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 493:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 798 .loc 1 493 1 799 001c 00BF nop 800 001e 80BD pop {r7, pc} 801 .L48: 802 .align 2 803 .L47: 804 0020 003C0140 .word 1073822720 805 .cfi_endproc 806 .LFE246: 808 .section .text.HAL_PWR_PVDCallback,"ax",%progbits 809 .align 1 810 .weak HAL_PWR_PVDCallback 811 .syntax unified 812 .thumb 813 .thumb_func 815 HAL_PWR_PVDCallback: 816 .LFB247: 494:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 495:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 496:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR PVD interrupt callback 497:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 498:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 499:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void) 500:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 817 .loc 1 500 1 818 .cfi_startproc 819 @ args = 0, pretend = 0, frame = 0 820 @ frame_needed = 1, uses_anonymous_args = 0 821 @ link register save eliminated. 822 0000 80B4 push {r7} 823 .LCFI60: 824 .cfi_def_cfa_offset 4 825 .cfi_offset 7, -4 826 0002 00AF add r7, sp, #0 827 .LCFI61: 828 .cfi_def_cfa_register 7 501:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed, 502:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file 503:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 504:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 829 .loc 1 504 1 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 24 830 0004 00BF nop 831 0006 BD46 mov sp, r7 832 .LCFI62: 833 .cfi_def_cfa_register 13 834 @ sp needed 835 0008 5DF8047B ldr r7, [sp], #4 836 .LCFI63: 837 .cfi_restore 7 838 .cfi_def_cfa_offset 0 839 000c 7047 bx lr 840 .cfi_endproc 841 .LFE247: 843 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits 844 .align 1 845 .global HAL_PWR_EnableSleepOnExit 846 .syntax unified 847 .thumb 848 .thumb_func 850 HAL_PWR_EnableSleepOnExit: 851 .LFB248: 505:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 506:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 507:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 508:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 509:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 510:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on 511:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * interruptions handling. 512:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 513:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 514:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) 515:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 852 .loc 1 515 1 853 .cfi_startproc 854 @ args = 0, pretend = 0, frame = 0 855 @ frame_needed = 1, uses_anonymous_args = 0 856 @ link register save eliminated. 857 0000 80B4 push {r7} 858 .LCFI64: 859 .cfi_def_cfa_offset 4 860 .cfi_offset 7, -4 861 0002 00AF add r7, sp, #0 862 .LCFI65: 863 .cfi_def_cfa_register 7 516:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ 517:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 864 .loc 1 517 3 865 0004 054B ldr r3, .L51 866 0006 1B69 ldr r3, [r3, #16] 867 0008 044A ldr r2, .L51 868 000a 43F00203 orr r3, r3, #2 869 000e 1361 str r3, [r2, #16] 518:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 870 .loc 1 518 1 871 0010 00BF nop 872 0012 BD46 mov sp, r7 873 .LCFI66: 874 .cfi_def_cfa_register 13 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 25 875 @ sp needed 876 0014 5DF8047B ldr r7, [sp], #4 877 .LCFI67: 878 .cfi_restore 7 879 .cfi_def_cfa_offset 0 880 0018 7047 bx lr 881 .L52: 882 001a 00BF .align 2 883 .L51: 884 001c 00ED00E0 .word -536810240 885 .cfi_endproc 886 .LFE248: 888 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits 889 .align 1 890 .global HAL_PWR_DisableSleepOnExit 891 .syntax unified 892 .thumb 893 .thumb_func 895 HAL_PWR_DisableSleepOnExit: 896 .LFB249: 519:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 520:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 521:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 522:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 523:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 524:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 525:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 526:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) 527:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 897 .loc 1 527 1 898 .cfi_startproc 899 @ args = 0, pretend = 0, frame = 0 900 @ frame_needed = 1, uses_anonymous_args = 0 901 @ link register save eliminated. 902 0000 80B4 push {r7} 903 .LCFI68: 904 .cfi_def_cfa_offset 4 905 .cfi_offset 7, -4 906 0002 00AF add r7, sp, #0 907 .LCFI69: 908 .cfi_def_cfa_register 7 528:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 529:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 909 .loc 1 529 3 910 0004 054B ldr r3, .L54 911 0006 1B69 ldr r3, [r3, #16] 912 0008 044A ldr r2, .L54 913 000a 23F00203 bic r3, r3, #2 914 000e 1361 str r3, [r2, #16] 530:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 915 .loc 1 530 1 916 0010 00BF nop 917 0012 BD46 mov sp, r7 918 .LCFI70: 919 .cfi_def_cfa_register 13 920 @ sp needed 921 0014 5DF8047B ldr r7, [sp], #4 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 26 922 .LCFI71: 923 .cfi_restore 7 924 .cfi_def_cfa_offset 0 925 0018 7047 bx lr 926 .L55: 927 001a 00BF .align 2 928 .L54: 929 001c 00ED00E0 .word -536810240 930 .cfi_endproc 931 .LFE249: 933 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits 934 .align 1 935 .global HAL_PWR_EnableSEVOnPend 936 .syntax unified 937 .thumb 938 .thumb_func 940 HAL_PWR_EnableSEVOnPend: 941 .LFB250: 531:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 532:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 533:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit. 534:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 535:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 536:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 537:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 538:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) 539:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 942 .loc 1 539 1 943 .cfi_startproc 944 @ args = 0, pretend = 0, frame = 0 945 @ frame_needed = 1, uses_anonymous_args = 0 946 @ link register save eliminated. 947 0000 80B4 push {r7} 948 .LCFI72: 949 .cfi_def_cfa_offset 4 950 .cfi_offset 7, -4 951 0002 00AF add r7, sp, #0 952 .LCFI73: 953 .cfi_def_cfa_register 7 540:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ 541:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 954 .loc 1 541 3 955 0004 054B ldr r3, .L57 956 0006 1B69 ldr r3, [r3, #16] 957 0008 044A ldr r2, .L57 958 000a 43F01003 orr r3, r3, #16 959 000e 1361 str r3, [r2, #16] 542:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 960 .loc 1 542 1 961 0010 00BF nop 962 0012 BD46 mov sp, r7 963 .LCFI74: 964 .cfi_def_cfa_register 13 965 @ sp needed 966 0014 5DF8047B ldr r7, [sp], #4 967 .LCFI75: 968 .cfi_restore 7 ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 27 969 .cfi_def_cfa_offset 0 970 0018 7047 bx lr 971 .L58: 972 001a 00BF .align 2 973 .L57: 974 001c 00ED00E0 .word -536810240 975 .cfi_endproc 976 .LFE250: 978 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits 979 .align 1 980 .global HAL_PWR_DisableSEVOnPend 981 .syntax unified 982 .thumb 983 .thumb_func 985 HAL_PWR_DisableSEVOnPend: 986 .LFB251: 543:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 544:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 545:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit. 546:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 547:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 548:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 549:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 550:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) 551:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 987 .loc 1 551 1 988 .cfi_startproc 989 @ args = 0, pretend = 0, frame = 0 990 @ frame_needed = 1, uses_anonymous_args = 0 991 @ link register save eliminated. 992 0000 80B4 push {r7} 993 .LCFI76: 994 .cfi_def_cfa_offset 4 995 .cfi_offset 7, -4 996 0002 00AF add r7, sp, #0 997 .LCFI77: 998 .cfi_def_cfa_register 7 552:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ 553:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 999 .loc 1 553 3 1000 0004 054B ldr r3, .L60 1001 0006 1B69 ldr r3, [r3, #16] 1002 0008 044A ldr r2, .L60 1003 000a 23F01003 bic r3, r3, #16 1004 000e 1361 str r3, [r2, #16] 554:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 1005 .loc 1 554 1 1006 0010 00BF nop 1007 0012 BD46 mov sp, r7 1008 .LCFI78: 1009 .cfi_def_cfa_register 13 1010 @ sp needed 1011 0014 5DF8047B ldr r7, [sp], #4 1012 .LCFI79: 1013 .cfi_restore 7 1014 .cfi_def_cfa_offset 0 1015 0018 7047 bx lr ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 28 1016 .L61: 1017 001a 00BF .align 2 1018 .L60: 1019 001c 00ED00E0 .word -536810240 1020 .cfi_endproc 1021 .LFE251: 1023 .text 1024 .Letext0: 1025 .file 2 "d:\\arm-gcc\\arm-none-eabi\\include\\machine\\_default_types.h" 1026 .file 3 "d:\\arm-gcc\\arm-none-eabi\\include\\sys\\_stdint.h" 1027 .file 4 "Drivers/CMSIS/Include/core_cm4.h" 1028 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h" 1029 .file 6 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" 1030 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h" ARM GAS C:\Users\10728\AppData\Local\Temp\cc14pPIS.s page 29 DEFINED SYMBOLS *ABS*:00000000 stm32f4xx_hal_pwr.c C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:20 .text.HAL_PWR_DeInit:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:26 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:67 .text.HAL_PWR_DeInit:00000028 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:72 .text.HAL_PWR_EnableBkUpAccess:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:78 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:124 .text.HAL_PWR_EnableBkUpAccess:00000020 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:130 .text.HAL_PWR_DisableBkUpAccess:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:136 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:182 .text.HAL_PWR_DisableBkUpAccess:00000020 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:188 .text.HAL_PWR_ConfigPVD:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:194 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:322 .text.HAL_PWR_ConfigPVD:000000b8 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:328 .text.HAL_PWR_EnablePVD:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:334 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:367 .text.HAL_PWR_EnablePVD:00000014 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:372 .text.HAL_PWR_DisablePVD:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:378 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:411 .text.HAL_PWR_DisablePVD:00000014 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:416 .text.HAL_PWR_EnableWakeUpPin:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:422 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:464 .text.HAL_PWR_EnableWakeUpPin:00000020 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:469 .text.HAL_PWR_DisableWakeUpPin:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:475 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:518 .text.HAL_PWR_DisableWakeUpPin:00000024 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:523 .text.HAL_PWR_EnterSLEEPMode:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:529 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:602 .text.HAL_PWR_EnterSLEEPMode:00000034 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:607 .text.HAL_PWR_EnterSTOPMode:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:613 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:699 .text.HAL_PWR_EnterSTOPMode:00000050 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:705 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:711 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:758 .text.HAL_PWR_EnterSTANDBYMode:00000028 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:764 .text.HAL_PWR_PVD_IRQHandler:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:770 .text.HAL_PWR_PVD_IRQHandler:00000000 HAL_PWR_PVD_IRQHandler C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:815 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:804 .text.HAL_PWR_PVD_IRQHandler:00000020 $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:809 .text.HAL_PWR_PVDCallback:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:844 .text.HAL_PWR_EnableSleepOnExit:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:850 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:884 .text.HAL_PWR_EnableSleepOnExit:0000001c $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:889 .text.HAL_PWR_DisableSleepOnExit:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:895 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:929 .text.HAL_PWR_DisableSleepOnExit:0000001c $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:934 .text.HAL_PWR_EnableSEVOnPend:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:940 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:974 .text.HAL_PWR_EnableSEVOnPend:0000001c $d C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:979 .text.HAL_PWR_DisableSEVOnPend:00000000 $t C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:985 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend C:\Users\10728\AppData\Local\Temp\cc14pPIS.s:1019 .text.HAL_PWR_DisableSEVOnPend:0000001c $d NO UNDEFINED SYMBOLS