stm32l4xx_hal_pwr.c 24 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_hal_pwr.c
  4. * @author MCD Application Team
  5. * @brief PWR HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Power Controller (PWR) peripheral:
  8. * + Initialization/de-initialization functions
  9. * + Peripheral Control functions
  10. *
  11. ******************************************************************************
  12. * @attention
  13. *
  14. * Copyright (c) 2019 STMicroelectronics.
  15. * All rights reserved.
  16. *
  17. * This software is licensed under terms that can be found in the LICENSE file
  18. * in the root directory of this software component.
  19. * If no LICENSE file comes with this software, it is provided AS-IS.
  20. *
  21. ******************************************************************************
  22. */
  23. /* Includes ------------------------------------------------------------------*/
  24. #include "stm32l4xx_hal.h"
  25. /** @addtogroup STM32L4xx_HAL_Driver
  26. * @{
  27. */
  28. /** @defgroup PWR PWR
  29. * @brief PWR HAL module driver
  30. * @{
  31. */
  32. #ifdef HAL_PWR_MODULE_ENABLED
  33. /* Private typedef -----------------------------------------------------------*/
  34. /* Private define ------------------------------------------------------------*/
  35. /** @defgroup PWR_Private_Defines PWR Private Defines
  36. * @{
  37. */
  38. /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
  39. * @{
  40. */
  41. #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
  42. #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
  43. #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
  44. #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
  45. /**
  46. * @}
  47. */
  48. /**
  49. * @}
  50. */
  51. /* Private macro -------------------------------------------------------------*/
  52. /* Private variables ---------------------------------------------------------*/
  53. /* Private function prototypes -----------------------------------------------*/
  54. /* Exported functions --------------------------------------------------------*/
  55. /** @defgroup PWR_Exported_Functions PWR Exported Functions
  56. * @{
  57. */
  58. /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
  59. * @brief Initialization and de-initialization functions
  60. *
  61. @verbatim
  62. ===============================================================================
  63. ##### Initialization and de-initialization functions #####
  64. ===============================================================================
  65. [..]
  66. @endverbatim
  67. * @{
  68. */
  69. /**
  70. * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
  71. * @retval None
  72. */
  73. void HAL_PWR_DeInit(void)
  74. {
  75. __HAL_RCC_PWR_FORCE_RESET();
  76. __HAL_RCC_PWR_RELEASE_RESET();
  77. }
  78. /**
  79. * @brief Enable access to the backup domain
  80. * (RTC registers, RTC backup data registers).
  81. * @note After reset, the backup domain is protected against
  82. * possible unwanted write accesses.
  83. * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
  84. * In order to set or modify the RTC clock, the backup domain access must be
  85. * disabled.
  86. * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
  87. * back-up domain.
  88. * @retval None
  89. */
  90. void HAL_PWR_EnableBkUpAccess(void)
  91. {
  92. SET_BIT(PWR->CR1, PWR_CR1_DBP);
  93. }
  94. /**
  95. * @brief Disable access to the backup domain
  96. * (RTC registers, RTC backup data registers).
  97. * @retval None
  98. */
  99. void HAL_PWR_DisableBkUpAccess(void)
  100. {
  101. CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
  102. }
  103. /**
  104. * @}
  105. */
  106. /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
  107. * @brief Low Power modes configuration functions
  108. *
  109. @verbatim
  110. ===============================================================================
  111. ##### Peripheral Control functions #####
  112. ===============================================================================
  113. [..]
  114. *** PVD configuration ***
  115. =========================
  116. [..]
  117. (+) The PVD is used to monitor the VDD power supply by comparing it to a
  118. threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
  119. (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
  120. than the PVD threshold. This event is internally connected to the EXTI
  121. line16 and can generate an interrupt if enabled. This is done through
  122. __HAL_PVD_EXTI_ENABLE_IT() macro.
  123. (+) The PVD is stopped in Standby mode.
  124. *** WakeUp pin configuration ***
  125. ================================
  126. [..]
  127. (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
  128. The polarity of these pins can be set to configure event detection on high
  129. level (rising edge) or low level (falling edge).
  130. *** Low Power modes configuration ***
  131. =====================================
  132. [..]
  133. The devices feature 8 low-power modes:
  134. (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
  135. (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
  136. (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
  137. (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
  138. (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
  139. (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
  140. (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
  141. (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
  142. (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
  143. *** Low-power run mode ***
  144. ==========================
  145. [..]
  146. (+) Entry: (from main run mode)
  147. (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
  148. (+) Exit:
  149. (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
  150. then can the system clock frequency be increased above 2 MHz.
  151. *** Sleep mode / Low-power sleep mode ***
  152. =========================================
  153. [..]
  154. (+) Entry:
  155. The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
  156. in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
  157. (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
  158. (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
  159. In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
  160. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  161. (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  162. (+) WFI Exit:
  163. (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
  164. controller (NVIC) or any wake-up event.
  165. (+) WFE Exit:
  166. (++) Any wake-up event such as an EXTI line configured in event mode.
  167. [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
  168. the MCU is in Low-power Run mode.
  169. *** Stop 0, Stop 1 and Stop 2 modes ***
  170. ===============================
  171. [..]
  172. (+) Entry:
  173. The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
  174. (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
  175. (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
  176. (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
  177. (++) PWR_MAINREGULATOR_ON
  178. (++) PWR_LOWPOWERREGULATOR_ON
  179. (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
  180. (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
  181. (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
  182. (+) WFI Exit:
  183. (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
  184. (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
  185. when programmed in wakeup mode.
  186. (+) WFE Exit:
  187. (++) Any EXTI Line (Internal or External) configured in Event mode.
  188. [..]
  189. When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
  190. depending on the LPR bit setting.
  191. When exiting Stop 2 mode, the MCU is in Run mode.
  192. *** Standby mode ***
  193. ====================
  194. [..]
  195. The Standby mode offers two options:
  196. (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
  197. SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
  198. and Standby circuitry.
  199. (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
  200. SRAM and register contents are lost except for the RTC registers, RTC backup registers
  201. and Standby circuitry.
  202. (++) Entry:
  203. (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
  204. SRAM1 and register contents are lost except for registers in the Backup domain and
  205. Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
  206. To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
  207. to set RRS bit.
  208. (++) Exit:
  209. (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
  210. external reset in NRST pin, IWDG reset.
  211. [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
  212. *** Shutdown mode ***
  213. ======================
  214. [..]
  215. In Shutdown mode,
  216. voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
  217. SRAM and registers contents are lost except for backup domain registers.
  218. (+) Entry:
  219. The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
  220. (+) Exit:
  221. (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
  222. external reset in NRST pin.
  223. [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
  224. *** Auto-wakeup (AWU) from low-power mode ***
  225. =============================================
  226. [..]
  227. The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
  228. Wakeup event, a tamper event or a time-stamp event, without depending on
  229. an external interrupt (Auto-wakeup mode).
  230. (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
  231. (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
  232. configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
  233. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
  234. is necessary to configure the RTC to detect the tamper or time stamp event using the
  235. HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
  236. (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
  237. configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
  238. @endverbatim
  239. * @{
  240. */
  241. /**
  242. * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
  243. * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
  244. * configuration information.
  245. * @note Refer to the electrical characteristics of your device datasheet for
  246. * more details about the voltage thresholds corresponding to each
  247. * detection level.
  248. * @retval None
  249. */
  250. HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
  251. {
  252. /* Check the parameters */
  253. assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
  254. assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
  255. /* Set PLS bits according to PVDLevel value */
  256. MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
  257. /* Clear any previous config. Keep it clear if no event or IT mode is selected */
  258. __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
  259. __HAL_PWR_PVD_EXTI_DISABLE_IT();
  260. __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
  261. __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
  262. /* Configure interrupt mode */
  263. if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
  264. {
  265. __HAL_PWR_PVD_EXTI_ENABLE_IT();
  266. }
  267. /* Configure event mode */
  268. if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
  269. {
  270. __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
  271. }
  272. /* Configure the edge */
  273. if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
  274. {
  275. __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
  276. }
  277. if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
  278. {
  279. __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
  280. }
  281. return HAL_OK;
  282. }
  283. /**
  284. * @brief Enable the Power Voltage Detector (PVD).
  285. * @retval None
  286. */
  287. void HAL_PWR_EnablePVD(void)
  288. {
  289. SET_BIT(PWR->CR2, PWR_CR2_PVDE);
  290. }
  291. /**
  292. * @brief Disable the Power Voltage Detector (PVD).
  293. * @retval None
  294. */
  295. void HAL_PWR_DisablePVD(void)
  296. {
  297. CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
  298. }
  299. /**
  300. * @brief Enable the WakeUp PINx functionality.
  301. * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
  302. * This parameter can be one of the following legacy values which set the default polarity
  303. * i.e. detection on high level (rising edge):
  304. * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
  305. *
  306. * or one of the following value where the user can explicitly specify the enabled pin and
  307. * the chosen polarity:
  308. * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
  309. * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
  310. * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
  311. * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
  312. * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
  313. * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
  314. * @retval None
  315. */
  316. void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
  317. {
  318. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
  319. /* Specifies the Wake-Up pin polarity for the event detection
  320. (rising or falling edge) */
  321. MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
  322. /* Enable wake-up pin */
  323. SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
  324. }
  325. /**
  326. * @brief Disable the WakeUp PINx functionality.
  327. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
  328. * This parameter can be one of the following values:
  329. * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
  330. * @retval None
  331. */
  332. void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
  333. {
  334. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  335. CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
  336. }
  337. /**
  338. * @brief Enter Sleep or Low-power Sleep mode.
  339. * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
  340. * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
  341. * This parameter can be one of the following values:
  342. * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
  343. * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
  344. * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
  345. * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
  346. * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
  347. * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
  348. * Additionally, the clock frequency must be reduced below 2 MHz.
  349. * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
  350. * be done before calling HAL_PWR_EnterSLEEPMode() API.
  351. * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
  352. * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
  353. * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
  354. * This parameter can be one of the following values:
  355. * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
  356. * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
  357. * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
  358. * the interrupt wake up source.
  359. * @retval None
  360. */
  361. void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
  362. {
  363. /* Check the parameters */
  364. assert_param(IS_PWR_REGULATOR(Regulator));
  365. assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
  366. /* Set Regulator parameter */
  367. if (Regulator == PWR_MAINREGULATOR_ON)
  368. {
  369. /* If in low-power run mode at this point, exit it */
  370. if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
  371. {
  372. if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
  373. {
  374. return ;
  375. }
  376. }
  377. /* Regulator now in main mode. */
  378. }
  379. else
  380. {
  381. /* If in run mode, first move to low-power run mode.
  382. The system clock frequency must be below 2 MHz at this point. */
  383. if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
  384. {
  385. HAL_PWREx_EnableLowPowerRunMode();
  386. }
  387. }
  388. /* Clear SLEEPDEEP bit of Cortex System Control Register */
  389. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  390. /* Select SLEEP mode entry -------------------------------------------------*/
  391. if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
  392. {
  393. /* Request Wait For Interrupt */
  394. __WFI();
  395. }
  396. else
  397. {
  398. /* Request Wait For Event */
  399. __SEV();
  400. __WFE();
  401. __WFE();
  402. }
  403. }
  404. /**
  405. * @brief Enter Stop mode
  406. * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
  407. * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
  408. * @note In Stop mode, all I/O pins keep the same state as in Run mode.
  409. * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
  410. * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
  411. * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
  412. * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
  413. * only to the peripheral requesting it.
  414. * SRAM1, SRAM2 and register contents are preserved.
  415. * The BOR is available.
  416. * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
  417. * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
  418. * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
  419. * is set; the MSI oscillator is selected if STOPWUCK is cleared.
  420. * @note When the voltage regulator operates in low power mode (Stop 1), an additional
  421. * startup delay is incurred when waking up.
  422. * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
  423. * is higher although the startup time is reduced.
  424. * @param Regulator: Specifies the regulator state in Stop mode.
  425. * This parameter can be one of the following values:
  426. * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
  427. * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
  428. * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
  429. * This parameter can be one of the following values:
  430. * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
  431. * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
  432. * @retval None
  433. */
  434. void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
  435. {
  436. /* Check the parameters */
  437. assert_param(IS_PWR_REGULATOR(Regulator));
  438. if(Regulator == PWR_LOWPOWERREGULATOR_ON)
  439. {
  440. HAL_PWREx_EnterSTOP1Mode(STOPEntry);
  441. }
  442. else
  443. {
  444. HAL_PWREx_EnterSTOP0Mode(STOPEntry);
  445. }
  446. }
  447. /**
  448. * @brief Enter Standby mode.
  449. * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
  450. * off. The voltage regulator is disabled, except when SRAM2 content is preserved
  451. * in which case the regulator is in low-power mode.
  452. * SRAM1 and register contents are lost except for registers in the Backup domain and
  453. * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
  454. * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
  455. * to set RRS bit.
  456. * The BOR is available.
  457. * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
  458. * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
  459. * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
  460. * same.
  461. * These states are effective in Standby mode only if APC bit is set through
  462. * HAL_PWREx_EnablePullUpPullDownConfig() API.
  463. * @retval None
  464. */
  465. void HAL_PWR_EnterSTANDBYMode(void)
  466. {
  467. /* Set Stand-by mode */
  468. MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
  469. /* Set SLEEPDEEP bit of Cortex System Control Register */
  470. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  471. /* This option is used to ensure that store operations are completed */
  472. #if defined ( __CC_ARM)
  473. __force_stores();
  474. #endif
  475. /* Request Wait For Interrupt */
  476. __WFI();
  477. }
  478. /**
  479. * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
  480. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  481. * re-enters SLEEP mode when an interruption handling is over.
  482. * Setting this bit is useful when the processor is expected to run only on
  483. * interruptions handling.
  484. * @retval None
  485. */
  486. void HAL_PWR_EnableSleepOnExit(void)
  487. {
  488. /* Set SLEEPONEXIT bit of Cortex System Control Register */
  489. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  490. }
  491. /**
  492. * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
  493. * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  494. * re-enters SLEEP mode when an interruption handling is over.
  495. * @retval None
  496. */
  497. void HAL_PWR_DisableSleepOnExit(void)
  498. {
  499. /* Clear SLEEPONEXIT bit of Cortex System Control Register */
  500. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  501. }
  502. /**
  503. * @brief Enable CORTEX M4 SEVONPEND bit.
  504. * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
  505. * WFE to wake up when an interrupt moves from inactive to pended.
  506. * @retval None
  507. */
  508. void HAL_PWR_EnableSEVOnPend(void)
  509. {
  510. /* Set SEVONPEND bit of Cortex System Control Register */
  511. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  512. }
  513. /**
  514. * @brief Disable CORTEX M4 SEVONPEND bit.
  515. * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
  516. * WFE to wake up when an interrupt moves from inactive to pended.
  517. * @retval None
  518. */
  519. void HAL_PWR_DisableSEVOnPend(void)
  520. {
  521. /* Clear SEVONPEND bit of Cortex System Control Register */
  522. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  523. }
  524. /**
  525. * @brief PWR PVD interrupt callback
  526. * @retval None
  527. */
  528. __weak void HAL_PWR_PVDCallback(void)
  529. {
  530. /* NOTE : This function should not be modified; when the callback is needed,
  531. the HAL_PWR_PVDCallback can be implemented in the user file
  532. */
  533. }
  534. /**
  535. * @}
  536. */
  537. /**
  538. * @}
  539. */
  540. #endif /* HAL_PWR_MODULE_ENABLED */
  541. /**
  542. * @}
  543. */
  544. /**
  545. * @}
  546. */