arm_const_structs.c 19 KB

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  1. /* ----------------------------------------------------------------------
  2. * Project: CMSIS DSP Library
  3. * Title: arm_const_structs.c
  4. * Description: Constant structs that are initialized for user convenience.
  5. * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions.
  6. *
  7. * $Date: 27. January 2017
  8. * $Revision: V.1.5.1
  9. *
  10. * Target Processor: Cortex-M cores
  11. * -------------------------------------------------------------------- */
  12. /*
  13. * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
  14. *
  15. * SPDX-License-Identifier: Apache-2.0
  16. *
  17. * Licensed under the Apache License, Version 2.0 (the License); you may
  18. * not use this file except in compliance with the License.
  19. * You may obtain a copy of the License at
  20. *
  21. * www.apache.org/licenses/LICENSE-2.0
  22. *
  23. * Unless required by applicable law or agreed to in writing, software
  24. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  25. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  26. * See the License for the specific language governing permissions and
  27. * limitations under the License.
  28. */
  29. #include "arm_const_structs.h"
  30. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
  31. /* Floating-point structs */
  32. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16))
  33. const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
  34. 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH
  35. };
  36. #endif
  37. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32))
  38. const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
  39. 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH
  40. };
  41. #endif
  42. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64))
  43. const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
  44. 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH
  45. };
  46. #endif
  47. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128))
  48. const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
  49. 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
  50. };
  51. #endif
  52. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256))
  53. const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
  54. 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
  55. };
  56. #endif
  57. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512))
  58. const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
  59. 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
  60. };
  61. #endif
  62. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024))
  63. const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
  64. 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH
  65. };
  66. #endif
  67. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048))
  68. const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
  69. 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH
  70. };
  71. #endif
  72. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096))
  73. const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
  74. 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE_4096_TABLE_LENGTH
  75. };
  76. #endif
  77. /* Fixed-point structs */
  78. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16))
  79. const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = {
  80. 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH
  81. };
  82. #endif
  83. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32))
  84. const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = {
  85. 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH
  86. };
  87. #endif
  88. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64))
  89. const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = {
  90. 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH
  91. };
  92. #endif
  93. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128))
  94. const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = {
  95. 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH
  96. };
  97. #endif
  98. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256))
  99. const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = {
  100. 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH
  101. };
  102. #endif
  103. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512))
  104. const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = {
  105. 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH
  106. };
  107. #endif
  108. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024))
  109. const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = {
  110. 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
  111. };
  112. #endif
  113. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048))
  114. const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = {
  115. 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
  116. };
  117. #endif
  118. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096))
  119. const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = {
  120. 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
  121. };
  122. #endif
  123. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16))
  124. const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = {
  125. 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH
  126. };
  127. #endif
  128. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32))
  129. const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = {
  130. 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH
  131. };
  132. #endif
  133. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64))
  134. const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = {
  135. 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH
  136. };
  137. #endif
  138. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128))
  139. const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = {
  140. 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH
  141. };
  142. #endif
  143. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256))
  144. const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = {
  145. 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH
  146. };
  147. #endif
  148. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512))
  149. const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = {
  150. 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH
  151. };
  152. #endif
  153. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024))
  154. const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = {
  155. 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
  156. };
  157. #endif
  158. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048))
  159. const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = {
  160. 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
  161. };
  162. #endif
  163. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096))
  164. const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = {
  165. 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
  166. };
  167. #endif
  168. /* Structure for real-value inputs */
  169. /* Floating-point structs */
  170. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32))
  171. const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len32 = {
  172. { 16, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_16_TABLE_LENGTH },
  173. 32U,
  174. (float32_t *)twiddleCoef_rfft_32
  175. };
  176. #endif
  177. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64))
  178. const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len64 = {
  179. { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH },
  180. 64U,
  181. (float32_t *)twiddleCoef_rfft_64
  182. };
  183. #endif
  184. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128))
  185. const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len128 = {
  186. { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH },
  187. 128U,
  188. (float32_t *)twiddleCoef_rfft_128
  189. };
  190. #endif
  191. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256))
  192. const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len256 = {
  193. { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH },
  194. 256U,
  195. (float32_t *)twiddleCoef_rfft_256
  196. };
  197. #endif
  198. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512))
  199. const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len512 = {
  200. { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH },
  201. 512U,
  202. (float32_t *)twiddleCoef_rfft_512
  203. };
  204. #endif
  205. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024))
  206. const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len1024 = {
  207. { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH },
  208. 1024U,
  209. (float32_t *)twiddleCoef_rfft_1024
  210. };
  211. #endif
  212. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048))
  213. const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len2048 = {
  214. { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH },
  215. 2048U,
  216. (float32_t *)twiddleCoef_rfft_2048
  217. };
  218. #endif
  219. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096))
  220. const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len4096 = {
  221. { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH },
  222. 4096U,
  223. (float32_t *)twiddleCoef_rfft_4096
  224. };
  225. #endif
  226. /* Fixed-point structs */
  227. /* q31_t */
  228. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16))
  229. const arm_rfft_instance_q31 arm_rfft_sR_q31_len32 = {
  230. 32U,
  231. 0,
  232. 1,
  233. 256U,
  234. (q31_t*)realCoefAQ31,
  235. (q31_t*)realCoefBQ31,
  236. &arm_cfft_sR_q31_len16
  237. };
  238. #endif
  239. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32))
  240. const arm_rfft_instance_q31 arm_rfft_sR_q31_len64 = {
  241. 64U,
  242. 0,
  243. 1,
  244. 128U,
  245. (q31_t*)realCoefAQ31,
  246. (q31_t*)realCoefBQ31,
  247. &arm_cfft_sR_q31_len32
  248. };
  249. #endif
  250. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64))
  251. const arm_rfft_instance_q31 arm_rfft_sR_q31_len128 = {
  252. 128U,
  253. 0,
  254. 1,
  255. 64U,
  256. (q31_t*)realCoefAQ31,
  257. (q31_t*)realCoefBQ31,
  258. &arm_cfft_sR_q31_len64
  259. };
  260. #endif
  261. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128))
  262. const arm_rfft_instance_q31 arm_rfft_sR_q31_len256 = {
  263. 256U,
  264. 0,
  265. 1,
  266. 32U,
  267. (q31_t*)realCoefAQ31,
  268. (q31_t*)realCoefBQ31,
  269. &arm_cfft_sR_q31_len128
  270. };
  271. #endif
  272. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256))
  273. const arm_rfft_instance_q31 arm_rfft_sR_q31_len512 = {
  274. 512U,
  275. 0,
  276. 1,
  277. 16U,
  278. (q31_t*)realCoefAQ31,
  279. (q31_t*)realCoefBQ31,
  280. &arm_cfft_sR_q31_len256
  281. };
  282. #endif
  283. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512))
  284. const arm_rfft_instance_q31 arm_rfft_sR_q31_len1024 = {
  285. 1024U,
  286. 0,
  287. 1,
  288. 8U,
  289. (q31_t*)realCoefAQ31,
  290. (q31_t*)realCoefBQ31,
  291. &arm_cfft_sR_q31_len512
  292. };
  293. #endif
  294. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024))
  295. const arm_rfft_instance_q31 arm_rfft_sR_q31_len2048 = {
  296. 2048U,
  297. 0,
  298. 1,
  299. 4U,
  300. (q31_t*)realCoefAQ31,
  301. (q31_t*)realCoefBQ31,
  302. &arm_cfft_sR_q31_len1024
  303. };
  304. #endif
  305. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048))
  306. const arm_rfft_instance_q31 arm_rfft_sR_q31_len4096 = {
  307. 4096U,
  308. 0,
  309. 1,
  310. 2U,
  311. (q31_t*)realCoefAQ31,
  312. (q31_t*)realCoefBQ31,
  313. &arm_cfft_sR_q31_len2048
  314. };
  315. #endif
  316. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096))
  317. const arm_rfft_instance_q31 arm_rfft_sR_q31_len8192 = {
  318. 8192U,
  319. 0,
  320. 1,
  321. 1U,
  322. (q31_t*)realCoefAQ31,
  323. (q31_t*)realCoefBQ31,
  324. &arm_cfft_sR_q31_len4096
  325. };
  326. #endif
  327. /* q15_t */
  328. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16))
  329. const arm_rfft_instance_q15 arm_rfft_sR_q15_len32 = {
  330. 32U,
  331. 0,
  332. 1,
  333. 256U,
  334. (q15_t*)realCoefAQ15,
  335. (q15_t*)realCoefBQ15,
  336. &arm_cfft_sR_q15_len16
  337. };
  338. #endif
  339. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32))
  340. const arm_rfft_instance_q15 arm_rfft_sR_q15_len64 = {
  341. 64U,
  342. 0,
  343. 1,
  344. 128U,
  345. (q15_t*)realCoefAQ15,
  346. (q15_t*)realCoefBQ15,
  347. &arm_cfft_sR_q15_len32
  348. };
  349. #endif
  350. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64))
  351. const arm_rfft_instance_q15 arm_rfft_sR_q15_len128 = {
  352. 128U,
  353. 0,
  354. 1,
  355. 64U,
  356. (q15_t*)realCoefAQ15,
  357. (q15_t*)realCoefBQ15,
  358. &arm_cfft_sR_q15_len64
  359. };
  360. #endif
  361. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128))
  362. const arm_rfft_instance_q15 arm_rfft_sR_q15_len256 = {
  363. 256U,
  364. 0,
  365. 1,
  366. 32U,
  367. (q15_t*)realCoefAQ15,
  368. (q15_t*)realCoefBQ15,
  369. &arm_cfft_sR_q15_len128
  370. };
  371. #endif
  372. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256))
  373. const arm_rfft_instance_q15 arm_rfft_sR_q15_len512 = {
  374. 512U,
  375. 0,
  376. 1,
  377. 16U,
  378. (q15_t*)realCoefAQ15,
  379. (q15_t*)realCoefBQ15,
  380. &arm_cfft_sR_q15_len256
  381. };
  382. #endif
  383. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512))
  384. const arm_rfft_instance_q15 arm_rfft_sR_q15_len1024 = {
  385. 1024U,
  386. 0,
  387. 1,
  388. 8U,
  389. (q15_t*)realCoefAQ15,
  390. (q15_t*)realCoefBQ15,
  391. &arm_cfft_sR_q15_len512
  392. };
  393. #endif
  394. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024))
  395. const arm_rfft_instance_q15 arm_rfft_sR_q15_len2048 = {
  396. 2048U,
  397. 0,
  398. 1,
  399. 4U,
  400. (q15_t*)realCoefAQ15,
  401. (q15_t*)realCoefBQ15,
  402. &arm_cfft_sR_q15_len1024
  403. };
  404. #endif
  405. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048))
  406. const arm_rfft_instance_q15 arm_rfft_sR_q15_len4096 = {
  407. 4096U,
  408. 0,
  409. 1,
  410. 2U,
  411. (q15_t*)realCoefAQ15,
  412. (q15_t*)realCoefBQ15,
  413. &arm_cfft_sR_q15_len2048
  414. };
  415. #endif
  416. #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096))
  417. const arm_rfft_instance_q15 arm_rfft_sR_q15_len8192 = {
  418. 8192U,
  419. 0,
  420. 1,
  421. 1U,
  422. (q15_t*)realCoefAQ15,
  423. (q15_t*)realCoefBQ15,
  424. &arm_cfft_sR_q15_len4096
  425. };
  426. #endif
  427. #endif