stm32l4xx_hal_pcd.h 37 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_hal_pcd.h
  4. * @author MCD Application Team
  5. * @brief Header file of PCD HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * Copyright (c) 2017 STMicroelectronics.
  10. * All rights reserved.
  11. *
  12. * This software is licensed under terms that can be found in the LICENSE file
  13. * in the root directory of this software component.
  14. * If no LICENSE file comes with this software, it is provided AS-IS.
  15. *
  16. ******************************************************************************
  17. */
  18. /* Define to prevent recursive inclusion -------------------------------------*/
  19. #ifndef STM32L4xx_HAL_PCD_H
  20. #define STM32L4xx_HAL_PCD_H
  21. #ifdef __cplusplus
  22. extern "C" {
  23. #endif
  24. /* Includes ------------------------------------------------------------------*/
  25. #include "stm32l4xx_ll_usb.h"
  26. #if defined (USB) || defined (USB_OTG_FS)
  27. /** @addtogroup STM32L4xx_HAL_Driver
  28. * @{
  29. */
  30. /** @addtogroup PCD
  31. * @{
  32. */
  33. /* Exported types ------------------------------------------------------------*/
  34. /** @defgroup PCD_Exported_Types PCD Exported Types
  35. * @{
  36. */
  37. /**
  38. * @brief PCD State structure definition
  39. */
  40. typedef enum
  41. {
  42. HAL_PCD_STATE_RESET = 0x00,
  43. HAL_PCD_STATE_READY = 0x01,
  44. HAL_PCD_STATE_ERROR = 0x02,
  45. HAL_PCD_STATE_BUSY = 0x03,
  46. HAL_PCD_STATE_TIMEOUT = 0x04
  47. } PCD_StateTypeDef;
  48. /* Device LPM suspend state */
  49. typedef enum
  50. {
  51. LPM_L0 = 0x00, /* on */
  52. LPM_L1 = 0x01, /* LPM L1 sleep */
  53. LPM_L2 = 0x02, /* suspend */
  54. LPM_L3 = 0x03, /* off */
  55. } PCD_LPM_StateTypeDef;
  56. typedef enum
  57. {
  58. PCD_LPM_L0_ACTIVE = 0x00, /* on */
  59. PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
  60. } PCD_LPM_MsgTypeDef;
  61. typedef enum
  62. {
  63. PCD_BCD_ERROR = 0xFF,
  64. PCD_BCD_CONTACT_DETECTION = 0xFE,
  65. PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
  66. PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
  67. PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
  68. PCD_BCD_DISCOVERY_COMPLETED = 0x00,
  69. } PCD_BCD_MsgTypeDef;
  70. #if defined (USB)
  71. #endif /* defined (USB) */
  72. #if defined (USB_OTG_FS)
  73. typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
  74. typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
  75. typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
  76. #endif /* defined (USB_OTG_FS) */
  77. #if defined (USB)
  78. typedef USB_TypeDef PCD_TypeDef;
  79. typedef USB_CfgTypeDef PCD_InitTypeDef;
  80. typedef USB_EPTypeDef PCD_EPTypeDef;
  81. #endif /* defined (USB) */
  82. /**
  83. * @brief PCD Handle Structure definition
  84. */
  85. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  86. typedef struct __PCD_HandleTypeDef
  87. #else
  88. typedef struct
  89. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  90. {
  91. PCD_TypeDef *Instance; /*!< Register base address */
  92. PCD_InitTypeDef Init; /*!< PCD required parameters */
  93. __IO uint8_t USB_Address; /*!< USB Address */
  94. #if defined (USB_OTG_FS)
  95. PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
  96. PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
  97. #endif /* defined (USB_OTG_FS) */
  98. #if defined (USB)
  99. PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
  100. PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
  101. #endif /* defined (USB) */
  102. HAL_LockTypeDef Lock; /*!< PCD peripheral status */
  103. __IO PCD_StateTypeDef State; /*!< PCD communication state */
  104. __IO uint32_t ErrorCode; /*!< PCD Error code */
  105. uint32_t Setup[12]; /*!< Setup packet buffer */
  106. PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
  107. uint32_t BESL;
  108. uint32_t FrameNumber; /*!< Store Current Frame number */
  109. uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
  110. This parameter can be set to ENABLE or DISABLE */
  111. uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
  112. This parameter can be set to ENABLE or DISABLE */
  113. void *pData; /*!< Pointer to upper stack Handler */
  114. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  115. void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
  116. void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
  117. void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
  118. void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
  119. void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
  120. void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
  121. void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
  122. void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
  123. void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
  124. void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
  125. void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
  126. void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
  127. void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
  128. void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
  129. void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
  130. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  131. } PCD_HandleTypeDef;
  132. /**
  133. * @}
  134. */
  135. /* Include PCD HAL Extended module */
  136. #include "stm32l4xx_hal_pcd_ex.h"
  137. /* Exported constants --------------------------------------------------------*/
  138. /** @defgroup PCD_Exported_Constants PCD Exported Constants
  139. * @{
  140. */
  141. /** @defgroup PCD_Speed PCD Speed
  142. * @{
  143. */
  144. #define PCD_SPEED_FULL USBD_FS_SPEED
  145. /**
  146. * @}
  147. */
  148. /** @defgroup PCD_PHY_Module PCD PHY Module
  149. * @{
  150. */
  151. #define PCD_PHY_ULPI 1U
  152. #define PCD_PHY_EMBEDDED 2U
  153. #define PCD_PHY_UTMI 3U
  154. /**
  155. * @}
  156. */
  157. /** @defgroup PCD_Error_Code_definition PCD Error Code definition
  158. * @brief PCD Error Code definition
  159. * @{
  160. */
  161. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  162. #define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
  163. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  164. /**
  165. * @}
  166. */
  167. /**
  168. * @}
  169. */
  170. /* Exported macros -----------------------------------------------------------*/
  171. /** @defgroup PCD_Exported_Macros PCD Exported Macros
  172. * @brief macros to handle interrupts and specific clock configurations
  173. * @{
  174. */
  175. #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
  176. #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
  177. #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
  178. ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
  179. #if defined (USB_OTG_FS)
  180. #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
  181. #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
  182. #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
  183. *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
  184. #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
  185. *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
  186. #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
  187. ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
  188. #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
  189. #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
  190. #endif /* defined (USB_OTG_FS) */
  191. #if defined (USB)
  192. #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
  193. &= (uint16_t)(~(__INTERRUPT__)))
  194. #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
  195. #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
  196. #endif /* defined (USB) */
  197. /**
  198. * @}
  199. */
  200. /* Exported functions --------------------------------------------------------*/
  201. /** @addtogroup PCD_Exported_Functions PCD Exported Functions
  202. * @{
  203. */
  204. /* Initialization/de-initialization functions ********************************/
  205. /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
  206. * @{
  207. */
  208. HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
  209. HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
  210. void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
  211. void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
  212. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  213. /** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
  214. * @brief HAL USB OTG PCD Callback ID enumeration definition
  215. * @{
  216. */
  217. typedef enum
  218. {
  219. HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
  220. HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
  221. HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
  222. HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
  223. HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
  224. HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
  225. HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
  226. HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
  227. HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
  228. } HAL_PCD_CallbackIDTypeDef;
  229. /**
  230. * @}
  231. */
  232. /** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
  233. * @brief HAL USB OTG PCD Callback pointer definition
  234. * @{
  235. */
  236. typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
  237. typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
  238. typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
  239. typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
  240. typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
  241. typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
  242. typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
  243. /**
  244. * @}
  245. */
  246. HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
  247. pPCD_CallbackTypeDef pCallback);
  248. HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
  249. HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
  250. pPCD_DataOutStageCallbackTypeDef pCallback);
  251. HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
  252. HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
  253. pPCD_DataInStageCallbackTypeDef pCallback);
  254. HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
  255. HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
  256. pPCD_IsoOutIncpltCallbackTypeDef pCallback);
  257. HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
  258. HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
  259. pPCD_IsoInIncpltCallbackTypeDef pCallback);
  260. HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
  261. HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
  262. HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
  263. HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
  264. HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
  265. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  266. /**
  267. * @}
  268. */
  269. /* I/O operation functions ***************************************************/
  270. /* Non-Blocking mode: Interrupt */
  271. /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
  272. * @{
  273. */
  274. HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
  275. HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
  276. void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
  277. void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
  278. void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
  279. void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
  280. void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
  281. void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
  282. void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
  283. void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
  284. void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
  285. void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
  286. void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
  287. void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
  288. /**
  289. * @}
  290. */
  291. /* Peripheral Control functions **********************************************/
  292. /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
  293. * @{
  294. */
  295. HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
  296. HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
  297. HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
  298. HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
  299. HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  300. HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
  301. HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
  302. HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  303. HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  304. HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  305. HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  306. HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
  307. HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
  308. uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
  309. /**
  310. * @}
  311. */
  312. /* Peripheral State functions ************************************************/
  313. /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
  314. * @{
  315. */
  316. PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
  317. /**
  318. * @}
  319. */
  320. /**
  321. * @}
  322. */
  323. /* Private constants ---------------------------------------------------------*/
  324. /** @defgroup PCD_Private_Constants PCD Private Constants
  325. * @{
  326. */
  327. /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
  328. * @{
  329. */
  330. #if defined (USB_OTG_FS)
  331. #define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 17) /*!< USB FS EXTI Line WakeUp Interrupt */
  332. #endif /* defined (USB_OTG_FS) */
  333. #if defined (USB)
  334. #define USB_WAKEUP_EXTI_LINE (0x1U << 17) /*!< USB FS EXTI Line WakeUp Interrupt */
  335. #endif /* defined (USB) */
  336. /**
  337. * @}
  338. */
  339. #if defined (USB)
  340. /** @defgroup PCD_EP0_MPS PCD EP0 MPS
  341. * @{
  342. */
  343. #define PCD_EP0MPS_64 EP_MPS_64
  344. #define PCD_EP0MPS_32 EP_MPS_32
  345. #define PCD_EP0MPS_16 EP_MPS_16
  346. #define PCD_EP0MPS_08 EP_MPS_8
  347. /**
  348. * @}
  349. */
  350. /** @defgroup PCD_ENDP PCD ENDP
  351. * @{
  352. */
  353. #define PCD_ENDP0 0U
  354. #define PCD_ENDP1 1U
  355. #define PCD_ENDP2 2U
  356. #define PCD_ENDP3 3U
  357. #define PCD_ENDP4 4U
  358. #define PCD_ENDP5 5U
  359. #define PCD_ENDP6 6U
  360. #define PCD_ENDP7 7U
  361. /**
  362. * @}
  363. */
  364. /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
  365. * @{
  366. */
  367. #define PCD_SNG_BUF 0U
  368. #define PCD_DBL_BUF 1U
  369. /**
  370. * @}
  371. */
  372. #endif /* defined (USB) */
  373. /**
  374. * @}
  375. */
  376. #if defined (USB_OTG_FS)
  377. #ifndef USB_OTG_DOEPINT_OTEPSPR
  378. #define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
  379. #endif /* defined USB_OTG_DOEPINT_OTEPSPR */
  380. #ifndef USB_OTG_DOEPMSK_OTEPSPRM
  381. #define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
  382. #endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
  383. #ifndef USB_OTG_DOEPINT_NAK
  384. #define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
  385. #endif /* defined USB_OTG_DOEPINT_NAK */
  386. #ifndef USB_OTG_DOEPMSK_NAKM
  387. #define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
  388. #endif /* defined USB_OTG_DOEPMSK_NAKM */
  389. #ifndef USB_OTG_DOEPINT_STPKTRX
  390. #define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
  391. #endif /* defined USB_OTG_DOEPINT_STPKTRX */
  392. #ifndef USB_OTG_DOEPMSK_NYETM
  393. #define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
  394. #endif /* defined USB_OTG_DOEPMSK_NYETM */
  395. #endif /* defined (USB_OTG_FS) */
  396. /* Private macros ------------------------------------------------------------*/
  397. /** @defgroup PCD_Private_Macros PCD Private Macros
  398. * @{
  399. */
  400. #if defined (USB)
  401. /******************** Bit definition for USB_COUNTn_RX register *************/
  402. #define USB_CNTRX_NBLK_MSK (0x1FU << 10)
  403. #define USB_CNTRX_BLSIZE (0x1U << 15)
  404. /* SetENDPOINT */
  405. #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
  406. (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
  407. /* GetENDPOINT */
  408. #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
  409. /**
  410. * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
  411. * @param USBx USB peripheral instance register address.
  412. * @param bEpNum Endpoint Number.
  413. * @param wType Endpoint Type.
  414. * @retval None
  415. */
  416. #define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
  417. (PCD_SET_ENDPOINT((USBx), (bEpNum), \
  418. ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
  419. /**
  420. * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
  421. * @param USBx USB peripheral instance register address.
  422. * @param bEpNum Endpoint Number.
  423. * @retval Endpoint Type
  424. */
  425. #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
  426. /**
  427. * @brief free buffer used from the application realizing it to the line
  428. * toggles bit SW_BUF in the double buffered endpoint register
  429. * @param USBx USB device.
  430. * @param bEpNum, bDir
  431. * @retval None
  432. */
  433. #define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
  434. do { \
  435. if ((bDir) == 0U) \
  436. { \
  437. /* OUT double buffered endpoint */ \
  438. PCD_TX_DTOG((USBx), (bEpNum)); \
  439. } \
  440. else if ((bDir) == 1U) \
  441. { \
  442. /* IN double buffered endpoint */ \
  443. PCD_RX_DTOG((USBx), (bEpNum)); \
  444. } \
  445. } while(0)
  446. /**
  447. * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
  448. * @param USBx USB peripheral instance register address.
  449. * @param bEpNum Endpoint Number.
  450. * @param wState new state
  451. * @retval None
  452. */
  453. #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
  454. do { \
  455. uint16_t _wRegVal; \
  456. \
  457. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
  458. /* toggle first bit ? */ \
  459. if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
  460. { \
  461. _wRegVal ^= USB_EPTX_DTOG1; \
  462. } \
  463. /* toggle second bit ? */ \
  464. if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
  465. { \
  466. _wRegVal ^= USB_EPTX_DTOG2; \
  467. } \
  468. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  469. } while(0) /* PCD_SET_EP_TX_STATUS */
  470. /**
  471. * @brief sets the status for rx transfer (bits STAT_TX[1:0])
  472. * @param USBx USB peripheral instance register address.
  473. * @param bEpNum Endpoint Number.
  474. * @param wState new state
  475. * @retval None
  476. */
  477. #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
  478. do { \
  479. uint16_t _wRegVal; \
  480. \
  481. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
  482. /* toggle first bit ? */ \
  483. if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
  484. { \
  485. _wRegVal ^= USB_EPRX_DTOG1; \
  486. } \
  487. /* toggle second bit ? */ \
  488. if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
  489. { \
  490. _wRegVal ^= USB_EPRX_DTOG2; \
  491. } \
  492. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  493. } while(0) /* PCD_SET_EP_RX_STATUS */
  494. /**
  495. * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
  496. * @param USBx USB peripheral instance register address.
  497. * @param bEpNum Endpoint Number.
  498. * @param wStaterx new state.
  499. * @param wStatetx new state.
  500. * @retval None
  501. */
  502. #define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
  503. do { \
  504. uint16_t _wRegVal; \
  505. \
  506. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
  507. /* toggle first bit ? */ \
  508. if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
  509. { \
  510. _wRegVal ^= USB_EPRX_DTOG1; \
  511. } \
  512. /* toggle second bit ? */ \
  513. if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
  514. { \
  515. _wRegVal ^= USB_EPRX_DTOG2; \
  516. } \
  517. /* toggle first bit ? */ \
  518. if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
  519. { \
  520. _wRegVal ^= USB_EPTX_DTOG1; \
  521. } \
  522. /* toggle second bit ? */ \
  523. if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
  524. { \
  525. _wRegVal ^= USB_EPTX_DTOG2; \
  526. } \
  527. \
  528. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  529. } while(0) /* PCD_SET_EP_TXRX_STATUS */
  530. /**
  531. * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
  532. * /STAT_RX[1:0])
  533. * @param USBx USB peripheral instance register address.
  534. * @param bEpNum Endpoint Number.
  535. * @retval status
  536. */
  537. #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
  538. #define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
  539. /**
  540. * @brief sets directly the VALID tx/rx-status into the endpoint register
  541. * @param USBx USB peripheral instance register address.
  542. * @param bEpNum Endpoint Number.
  543. * @retval None
  544. */
  545. #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
  546. #define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
  547. /**
  548. * @brief checks stall condition in an endpoint.
  549. * @param USBx USB peripheral instance register address.
  550. * @param bEpNum Endpoint Number.
  551. * @retval TRUE = endpoint in stall condition.
  552. */
  553. #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
  554. #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
  555. /**
  556. * @brief set & clear EP_KIND bit.
  557. * @param USBx USB peripheral instance register address.
  558. * @param bEpNum Endpoint Number.
  559. * @retval None
  560. */
  561. #define PCD_SET_EP_KIND(USBx, bEpNum) \
  562. do { \
  563. uint16_t _wRegVal; \
  564. \
  565. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
  566. \
  567. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
  568. } while(0) /* PCD_SET_EP_KIND */
  569. #define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
  570. do { \
  571. uint16_t _wRegVal; \
  572. \
  573. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
  574. \
  575. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  576. } while(0) /* PCD_CLEAR_EP_KIND */
  577. /**
  578. * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
  579. * @param USBx USB peripheral instance register address.
  580. * @param bEpNum Endpoint Number.
  581. * @retval None
  582. */
  583. #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
  584. #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
  585. /**
  586. * @brief Sets/clears directly EP_KIND bit in the endpoint register.
  587. * @param USBx USB peripheral instance register address.
  588. * @param bEpNum Endpoint Number.
  589. * @retval None
  590. */
  591. #define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
  592. #define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
  593. /**
  594. * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
  595. * @param USBx USB peripheral instance register address.
  596. * @param bEpNum Endpoint Number.
  597. * @retval None
  598. */
  599. #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
  600. do { \
  601. uint16_t _wRegVal; \
  602. \
  603. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
  604. \
  605. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
  606. } while(0) /* PCD_CLEAR_RX_EP_CTR */
  607. #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
  608. do { \
  609. uint16_t _wRegVal; \
  610. \
  611. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
  612. \
  613. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
  614. } while(0) /* PCD_CLEAR_TX_EP_CTR */
  615. /**
  616. * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
  617. * @param USBx USB peripheral instance register address.
  618. * @param bEpNum Endpoint Number.
  619. * @retval None
  620. */
  621. #define PCD_RX_DTOG(USBx, bEpNum) \
  622. do { \
  623. uint16_t _wEPVal; \
  624. \
  625. _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
  626. \
  627. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
  628. } while(0) /* PCD_RX_DTOG */
  629. #define PCD_TX_DTOG(USBx, bEpNum) \
  630. do { \
  631. uint16_t _wEPVal; \
  632. \
  633. _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
  634. \
  635. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
  636. } while(0) /* PCD_TX_DTOG */
  637. /**
  638. * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
  639. * @param USBx USB peripheral instance register address.
  640. * @param bEpNum Endpoint Number.
  641. * @retval None
  642. */
  643. #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
  644. do { \
  645. uint16_t _wRegVal; \
  646. \
  647. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
  648. \
  649. if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
  650. { \
  651. PCD_RX_DTOG((USBx), (bEpNum)); \
  652. } \
  653. } while(0) /* PCD_CLEAR_RX_DTOG */
  654. #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
  655. do { \
  656. uint16_t _wRegVal; \
  657. \
  658. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
  659. \
  660. if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
  661. { \
  662. PCD_TX_DTOG((USBx), (bEpNum)); \
  663. } \
  664. } while(0) /* PCD_CLEAR_TX_DTOG */
  665. /**
  666. * @brief Sets address in an endpoint register.
  667. * @param USBx USB peripheral instance register address.
  668. * @param bEpNum Endpoint Number.
  669. * @param bAddr Address.
  670. * @retval None
  671. */
  672. #define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
  673. do { \
  674. uint16_t _wRegVal; \
  675. \
  676. _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
  677. \
  678. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  679. } while(0) /* PCD_SET_EP_ADDRESS */
  680. /**
  681. * @brief Gets address in an endpoint register.
  682. * @param USBx USB peripheral instance register address.
  683. * @param bEpNum Endpoint Number.
  684. * @retval None
  685. */
  686. #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
  687. #define PCD_EP_TX_CNT(USBx, bEpNum) \
  688. ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
  689. ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
  690. #define PCD_EP_RX_CNT(USBx, bEpNum) \
  691. ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
  692. ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
  693. /**
  694. * @brief sets address of the tx/rx buffer.
  695. * @param USBx USB peripheral instance register address.
  696. * @param bEpNum Endpoint Number.
  697. * @param wAddr address to be set (must be word aligned).
  698. * @retval None
  699. */
  700. #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
  701. do { \
  702. __IO uint16_t *_wRegVal; \
  703. uint32_t _wRegBase = (uint32_t)USBx; \
  704. \
  705. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  706. _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
  707. *_wRegVal = ((wAddr) >> 1) << 1; \
  708. } while(0) /* PCD_SET_EP_TX_ADDRESS */
  709. #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
  710. do { \
  711. __IO uint16_t *_wRegVal; \
  712. uint32_t _wRegBase = (uint32_t)USBx; \
  713. \
  714. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  715. _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
  716. *_wRegVal = ((wAddr) >> 1) << 1; \
  717. } while(0) /* PCD_SET_EP_RX_ADDRESS */
  718. /**
  719. * @brief Gets address of the tx/rx buffer.
  720. * @param USBx USB peripheral instance register address.
  721. * @param bEpNum Endpoint Number.
  722. * @retval address of the buffer.
  723. */
  724. #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
  725. #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
  726. /**
  727. * @brief Sets counter of rx buffer with no. of blocks.
  728. * @param pdwReg Register pointer
  729. * @param wCount Counter.
  730. * @param wNBlocks no. of Blocks.
  731. * @retval None
  732. */
  733. #define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
  734. do { \
  735. (wNBlocks) = (wCount) >> 5; \
  736. if (((wCount) & 0x1fU) == 0U) \
  737. { \
  738. (wNBlocks)--; \
  739. } \
  740. *(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
  741. } while(0) /* PCD_CALC_BLK32 */
  742. #define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
  743. do { \
  744. (wNBlocks) = (wCount) >> 1; \
  745. if (((wCount) & 0x1U) != 0U) \
  746. { \
  747. (wNBlocks)++; \
  748. } \
  749. *(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
  750. } while(0) /* PCD_CALC_BLK2 */
  751. #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
  752. do { \
  753. uint32_t wNBlocks; \
  754. \
  755. *(pdwReg) &= 0x3FFU; \
  756. \
  757. if ((wCount) == 0U) \
  758. { \
  759. *(pdwReg) |= USB_CNTRX_BLSIZE; \
  760. } \
  761. else if ((wCount) <= 62U) \
  762. { \
  763. PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
  764. } \
  765. else \
  766. { \
  767. PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
  768. } \
  769. } while(0) /* PCD_SET_EP_CNT_RX_REG */
  770. #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
  771. do { \
  772. uint32_t _wRegBase = (uint32_t)(USBx); \
  773. __IO uint16_t *pdwReg; \
  774. \
  775. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  776. pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
  777. PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
  778. } while(0)
  779. /**
  780. * @brief sets counter for the tx/rx buffer.
  781. * @param USBx USB peripheral instance register address.
  782. * @param bEpNum Endpoint Number.
  783. * @param wCount Counter value.
  784. * @retval None
  785. */
  786. #define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
  787. do { \
  788. uint32_t _wRegBase = (uint32_t)(USBx); \
  789. __IO uint16_t *_wRegVal; \
  790. \
  791. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  792. _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
  793. *_wRegVal = (uint16_t)(wCount); \
  794. } while(0)
  795. #define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
  796. do { \
  797. uint32_t _wRegBase = (uint32_t)(USBx); \
  798. __IO uint16_t *_wRegVal; \
  799. \
  800. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  801. _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
  802. PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
  803. } while(0)
  804. /**
  805. * @brief gets counter of the tx buffer.
  806. * @param USBx USB peripheral instance register address.
  807. * @param bEpNum Endpoint Number.
  808. * @retval Counter value
  809. */
  810. #define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
  811. #define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
  812. /**
  813. * @brief Sets buffer 0/1 address in a double buffer endpoint.
  814. * @param USBx USB peripheral instance register address.
  815. * @param bEpNum Endpoint Number.
  816. * @param wBuf0Addr buffer 0 address.
  817. * @retval Counter value
  818. */
  819. #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
  820. do { \
  821. PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
  822. } while(0) /* PCD_SET_EP_DBUF0_ADDR */
  823. #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
  824. do { \
  825. PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
  826. } while(0) /* PCD_SET_EP_DBUF1_ADDR */
  827. /**
  828. * @brief Sets addresses in a double buffer endpoint.
  829. * @param USBx USB peripheral instance register address.
  830. * @param bEpNum Endpoint Number.
  831. * @param wBuf0Addr: buffer 0 address.
  832. * @param wBuf1Addr = buffer 1 address.
  833. * @retval None
  834. */
  835. #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
  836. do { \
  837. PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
  838. PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
  839. } while(0) /* PCD_SET_EP_DBUF_ADDR */
  840. /**
  841. * @brief Gets buffer 0/1 address of a double buffer endpoint.
  842. * @param USBx USB peripheral instance register address.
  843. * @param bEpNum Endpoint Number.
  844. * @retval None
  845. */
  846. #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
  847. #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
  848. /**
  849. * @brief Gets buffer 0/1 address of a double buffer endpoint.
  850. * @param USBx USB peripheral instance register address.
  851. * @param bEpNum Endpoint Number.
  852. * @param bDir endpoint dir EP_DBUF_OUT = OUT
  853. * EP_DBUF_IN = IN
  854. * @param wCount: Counter value
  855. * @retval None
  856. */
  857. #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
  858. do { \
  859. if ((bDir) == 0U) \
  860. /* OUT endpoint */ \
  861. { \
  862. PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
  863. } \
  864. else \
  865. { \
  866. if ((bDir) == 1U) \
  867. { \
  868. /* IN endpoint */ \
  869. PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
  870. } \
  871. } \
  872. } while(0) /* SetEPDblBuf0Count*/
  873. #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
  874. do { \
  875. uint32_t _wBase = (uint32_t)(USBx); \
  876. __IO uint16_t *_wEPRegVal; \
  877. \
  878. if ((bDir) == 0U) \
  879. { \
  880. /* OUT endpoint */ \
  881. PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
  882. } \
  883. else \
  884. { \
  885. if ((bDir) == 1U) \
  886. { \
  887. /* IN endpoint */ \
  888. _wBase += (uint32_t)(USBx)->BTABLE; \
  889. _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
  890. *_wEPRegVal = (uint16_t)(wCount); \
  891. } \
  892. } \
  893. } while(0) /* SetEPDblBuf1Count */
  894. #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
  895. do { \
  896. PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
  897. PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
  898. } while(0) /* PCD_SET_EP_DBUF_CNT */
  899. /**
  900. * @brief Gets buffer 0/1 rx/tx counter for double buffering.
  901. * @param USBx USB peripheral instance register address.
  902. * @param bEpNum Endpoint Number.
  903. * @retval None
  904. */
  905. #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
  906. #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
  907. #endif /* defined (USB) */
  908. /**
  909. * @}
  910. */
  911. /**
  912. * @}
  913. */
  914. /**
  915. * @}
  916. */
  917. #endif /* defined (USB) || defined (USB_OTG_FS) */
  918. #ifdef __cplusplus
  919. }
  920. #endif
  921. #endif /* STM32L4xx_HAL_PCD_H */